From: Daniel Vetter <daniel@ffwll.ch>
To: Kenneth Graunke <kenneth@whitecape.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Allow reading the TIMESTAMP register on Gen8.
Date: Wed, 22 Jan 2014 10:48:45 +0100 [thread overview]
Message-ID: <20140122094845.GE9772@phenom.ffwll.local> (raw)
In-Reply-To: <1390344158-2191-1-git-send-email-kenneth@whitecape.org>
On Tue, Jan 21, 2014 at 02:42:38PM -0800, Kenneth Graunke wrote:
> Nothing's changed here; we just need to bump the generation check.
>
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Merged to -fixes to avoid hassles with ABI negotation - 3.14 is the first
officially supported bdw platform anyway.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 646fecf..c628414 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -805,7 +805,7 @@ static const struct register_whitelist {
> uint32_t size;
> uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
> } whitelist[] = {
> - { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
> + { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0x1F0 },
> };
>
> int i915_reg_read_ioctl(struct drm_device *dev,
> --
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
prev parent reply other threads:[~2014-01-22 9:48 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-21 22:42 [PATCH] drm/i915: Allow reading the TIMESTAMP register on Gen8 Kenneth Graunke
2014-01-22 9:48 ` Daniel Vetter [this message]
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