From: Will Deacon <will.deacon@arm.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Neil Leeder <nleeder@codeaurora.org>,
Ashwin Chaugule <ashwinc@codeaurora.org>
Subject: Re: [PATCH v2 5/7] ARM: perf_event: Fully support Krait CPU PMU events
Date: Thu, 23 Jan 2014 10:32:16 +0000 [thread overview]
Message-ID: <20140123103216.GC5466@mudshark.cambridge.arm.com> (raw)
In-Reply-To: <52E02E7E.4050203@codeaurora.org>
On Wed, Jan 22, 2014 at 08:47:58PM +0000, Stephen Boyd wrote:
> On 01/21/14 10:37, Stephen Boyd wrote:
> > On 01/21/14 10:07, Will Deacon wrote:
> >> Do you need isbs to ensure the pmresrn side-effects have happened, or are
> >> the registers self-synchronising? Similarly for your other IMP DEF
> >> registers.
> > There aren't any isbs in the downstream android sources so I assume
> > they're self synchronizing. I'll confirm with the CPU designers to make
> > sure.
> >
>
> CPU folks say no need for isb.
Good, good!
> They mentioned that the lack of an isb after the
> armv7_pmnc_enable_counter() call will leave the action of enabling the
> counter "in-flight". The window is probably pretty short on an SMP kernel
> because of the spin_unlock right after with the barriers in it, but the
> same can't be said for a UP kernel.
Yep, we rely on the exception return for that.
> Also, the fuzzer didn't find anything else, but I found a bug in the
> bitmap logic, updated and reran the fuzzer this morning. Everything
> looks good.
Okey doke, I guess if you can repost at -rc1 then I can look at pulling
this into my tree.
Cheers,
Will
WARNING: multiple messages have this Message-ID (diff)
From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 5/7] ARM: perf_event: Fully support Krait CPU PMU events
Date: Thu, 23 Jan 2014 10:32:16 +0000 [thread overview]
Message-ID: <20140123103216.GC5466@mudshark.cambridge.arm.com> (raw)
In-Reply-To: <52E02E7E.4050203@codeaurora.org>
On Wed, Jan 22, 2014 at 08:47:58PM +0000, Stephen Boyd wrote:
> On 01/21/14 10:37, Stephen Boyd wrote:
> > On 01/21/14 10:07, Will Deacon wrote:
> >> Do you need isbs to ensure the pmresrn side-effects have happened, or are
> >> the registers self-synchronising? Similarly for your other IMP DEF
> >> registers.
> > There aren't any isbs in the downstream android sources so I assume
> > they're self synchronizing. I'll confirm with the CPU designers to make
> > sure.
> >
>
> CPU folks say no need for isb.
Good, good!
> They mentioned that the lack of an isb after the
> armv7_pmnc_enable_counter() call will leave the action of enabling the
> counter "in-flight". The window is probably pretty short on an SMP kernel
> because of the spin_unlock right after with the barriers in it, but the
> same can't be said for a UP kernel.
Yep, we rely on the exception return for that.
> Also, the fuzzer didn't find anything else, but I found a bug in the
> bitmap logic, updated and reran the fuzzer this morning. Everything
> looks good.
Okey doke, I guess if you can repost at -rc1 then I can look at pulling
this into my tree.
Cheers,
Will
next prev parent reply other threads:[~2014-01-23 10:32 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-15 17:55 [PATCH v2 0/7] Support Krait CPU PMUs Stephen Boyd
2014-01-15 17:55 ` Stephen Boyd
2014-01-15 17:55 ` [PATCH v2 1/7] ARM: perf_event: Support percpu irqs for the CPU PMU Stephen Boyd
2014-01-15 17:55 ` Stephen Boyd
2014-01-15 20:54 ` Stephen Boyd
2014-01-15 20:54 ` Stephen Boyd
2014-01-17 15:04 ` Will Deacon
2014-01-17 15:04 ` Will Deacon
2014-01-17 17:54 ` Stephen Boyd
2014-01-17 17:54 ` Stephen Boyd
2014-01-17 18:08 ` Will Deacon
2014-01-17 18:08 ` Will Deacon
2014-02-07 11:30 ` Will Deacon
2014-02-07 11:30 ` Will Deacon
2014-02-07 11:30 ` Will Deacon
2014-02-03 20:31 ` Christopher Covington
2014-02-03 20:31 ` Christopher Covington
2014-01-15 17:55 ` [PATCH v2 2/7] ARM: perf_event: Assign pdev pointer earlier for CPU PMUs Stephen Boyd
2014-01-15 17:55 ` Stephen Boyd
2014-01-15 17:55 ` [PATCH v2 3/7] ARM: perf_event: Add basic support for Krait " Stephen Boyd
2014-01-15 17:55 ` Stephen Boyd
2014-01-15 17:55 ` [PATCH v2 4/7] ARM: perf_event: Add hook for event index clearing Stephen Boyd
2014-01-15 17:55 ` Stephen Boyd
2014-01-15 17:55 ` [PATCH v2 5/7] ARM: perf_event: Fully support Krait CPU PMU events Stephen Boyd
2014-01-15 17:55 ` Stephen Boyd
2014-01-21 18:07 ` Will Deacon
2014-01-21 18:07 ` Will Deacon
2014-01-21 18:37 ` Stephen Boyd
2014-01-21 18:37 ` Stephen Boyd
2014-01-21 21:59 ` Stephen Boyd
2014-01-21 21:59 ` Stephen Boyd
2014-01-22 10:58 ` Will Deacon
2014-01-22 10:58 ` Will Deacon
2014-01-22 20:47 ` Stephen Boyd
2014-01-22 20:47 ` Stephen Boyd
2014-01-23 10:32 ` Will Deacon [this message]
2014-01-23 10:32 ` Will Deacon
[not found] ` <1389808535-23852-1-git-send-email-sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2014-01-15 17:55 ` [PATCH v2 6/7] devicetree: bindings: Document Krait performance monitor units (PMU) Stephen Boyd
2014-01-15 17:55 ` Stephen Boyd
2014-01-15 17:55 ` Stephen Boyd
2014-01-15 17:55 ` [PATCH v2 7/7] ARM: dts: msm: Add krait-pmu to platforms with Krait CPUs Stephen Boyd
2014-01-15 17:55 ` Stephen Boyd
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