Re: [Bug 68591] Regression: Asrock M3A UCC does not boot without acpi=off or pci=noacpi

Re: [Bug 68591] Regression: Asrock M3A UCC does not boot without acpi=off or pci=noacpi

[Bjorn Helgaas]

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[+cc linux-pci to make this more discoverable]

> https://bugzilla.kernel.org/show_bug.cgi?id=68591

  ACPI: HPET id: 0x43538301 base: 0xfed00000
  pci_root PNP0A03:00: host bridge window [mem 0xd0000000-0xdfffffff]
  pci_root PNP0A03:00: host bridge window [mem 0xf0000000-0xfebfffff]
  pci 0000:00:14.0: [1002:4385] type 0 class 0x000c05
  pci 0000:00:14.0: reg 14: [mem 0xfed00000-0xfed003ff]
  hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0
  pnp 00:06: Plug and Play ACPI device, IDs PNP0103 (active)
  pnp 00:06: [mem 0xfed00000-0xfed003ff]

The 00:14.0 MEM BAR is outside all the host bridge windows, so unless you
boot with "pci=nocrs", Linux will try to move it.  Moving it is not a good
idea because that's the HPET timer, and the rest of the kernel still
thinks it lives at 0xfed00000 because we learned that from the ACPI HPET
table.  It's also not a good thing that we have that resource reported for
both the PCI 00:14.0 device and the ACPI/PNP 00:06 device.

It looks like d7451fca18e2 ("x86, hpet: SB600 - remove HPET resources from
PCI device") is intended to fix this very problem by hiding BAR 1 of the
00:14.0 device, and I don't know why it isn't working on your system.  It
is interesting that the description of the bit toggled by the quirk (the
HideHpetBar bit in the SoftPciRst register at PM_Reg:55h, in the AMD SB600
Register Reference Manual, P/N 46155_sb600_rrg_pub_3.03) says "can not
write and always read 0".

Any chance you can try the attached patch?  It won't fix anything, so
you'll still have to boot with "pci=nocrs".

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diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index bca9e85daaa5..8e65dbdd61c6 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -512,14 +512,22 @@ static void sb600_disable_hpet_bar(struct pci_dev *dev)
 	 */
 
 	pci_read_config_byte(dev, 0x08, &val);
+	dev_info(&dev->dev, "cfg 0x08: %#02x\n", val);
 
 	if (val < 0x2F) {
+		dev_info(&dev->dev, "disabling BAR 1 (HPET address)\n");
 		outb(0x55, 0xCD6);
 		val = inb(0xCD7);
+		dev_info(&dev->dev, "PM  0x55: %#02x\n", val);
 
 		/* Set bit 7 in PM register 0x55 */
 		outb(0x55, 0xCD6);
 		outb(val | 0x80, 0xCD7);
+		dev_info(&dev->dev, "PM  0x55: wrote %#02x\n", val | 0x80);
+
+		outb(0x55, 0xCD6);
+		val = inb(0xCD7);
+		dev_info(&dev->dev, "PM  0x55: %#02x\n", val);
 	}
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);