From: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
To: Srikanth Thokala <sthokal@xilinx.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Arnd Bergmann <arnd@arndb.de>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
Michal Simek <michal.simek@xilinx.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Grant Likely <grant.likely@linaro.org>,
linux-arm <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] pcie: Add Xilinx PCIe Host Bridge IP driver
Date: Fri, 21 Feb 2014 09:28:24 -0700 [thread overview]
Message-ID: <20140221162824.GA4706@obsidianresearch.com> (raw)
In-Reply-To: <CA+mB=1L+QM2cKq==mwYesp=E7S2N-xTiN7AoBvbzAO2UMn0qVQ@mail.gmail.com>
On Fri, Feb 21, 2014 at 08:18:00PM +0530, Srikanth Thokala wrote:
> 00:00.0 Class 0604: Device 10ee:7081
So this is great, a root port bridge is exactly correct - I would
recommend using device 1 for this (device 0 is the host bridge in most
cases), but I don't think that has any functional impact.
> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> ParErr+ Stepping- SERR+ FastB2B- DisINTx-
> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
> Latency: 0, Cache Line Size: 64 bytes
> Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
> I/O behind bridge: 00000000-00000fff
> Memory behind bridge: 00000000-000fffff
> Prefetchable memory behind bridge: 00000000-000fffff
What is going on here? These ranges should match the MMIO aperture and
critically must enclose the downstream bars:
> 01:00.0 Class 0200: Device 14e4:1677 (rev 11)
> Region 0: Memory at 60000000 (64-bit, non-prefetchable) [size=64K]
> Expansion ROM at 60010000 [disabled] [size=64K]
So one of those two is not right..
Jason
WARNING: multiple messages have this Message-ID (diff)
From: jgunthorpe@obsidianresearch.com (Jason Gunthorpe)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] pcie: Add Xilinx PCIe Host Bridge IP driver
Date: Fri, 21 Feb 2014 09:28:24 -0700 [thread overview]
Message-ID: <20140221162824.GA4706@obsidianresearch.com> (raw)
In-Reply-To: <CA+mB=1L+QM2cKq==mwYesp=E7S2N-xTiN7AoBvbzAO2UMn0qVQ@mail.gmail.com>
On Fri, Feb 21, 2014 at 08:18:00PM +0530, Srikanth Thokala wrote:
> 00:00.0 Class 0604: Device 10ee:7081
So this is great, a root port bridge is exactly correct - I would
recommend using device 1 for this (device 0 is the host bridge in most
cases), but I don't think that has any functional impact.
> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> ParErr+ Stepping- SERR+ FastB2B- DisINTx-
> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
> Latency: 0, Cache Line Size: 64 bytes
> Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
> I/O behind bridge: 00000000-00000fff
> Memory behind bridge: 00000000-000fffff
> Prefetchable memory behind bridge: 00000000-000fffff
What is going on here? These ranges should match the MMIO aperture and
critically must enclose the downstream bars:
> 01:00.0 Class 0200: Device 14e4:1677 (rev 11)
> Region 0: Memory at 60000000 (64-bit, non-prefetchable) [size=64K]
> Expansion ROM at 60010000 [disabled] [size=64K]
So one of those two is not right..
Jason
next prev parent reply other threads:[~2014-02-21 16:28 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-16 15:33 [PATCH] pcie: Add Xilinx PCIe Host Bridge IP driver Srikanth Thokala
2014-02-16 15:33 ` Srikanth Thokala
2014-02-18 21:32 ` Bjorn Helgaas
2014-02-18 21:32 ` Bjorn Helgaas
2014-02-19 0:35 ` Jason Gunthorpe
2014-02-19 0:35 ` Jason Gunthorpe
2014-02-20 7:09 ` Srikanth Thokala
2014-02-20 7:09 ` Srikanth Thokala
2014-02-20 17:45 ` Jason Gunthorpe
2014-02-20 17:45 ` Jason Gunthorpe
2014-02-21 14:48 ` Srikanth Thokala
2014-02-21 14:48 ` Srikanth Thokala
2014-02-21 16:28 ` Jason Gunthorpe [this message]
2014-02-21 16:28 ` Jason Gunthorpe
2014-02-25 12:27 ` Srikanth Thokala
2014-02-25 12:27 ` Srikanth Thokala
2014-02-19 8:54 ` Michal Simek
2014-02-19 8:54 ` Michal Simek
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