From: "Michael S. Tsirkin" <mst@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-trivial@nongnu.org, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-trivial] [PATCH 01/12] target-i386: Avoid shifting left into sign bit
Date: Mon, 10 Mar 2014 23:57:38 +0200 [thread overview]
Message-ID: <20140310215738.GC7104@redhat.com> (raw)
In-Reply-To: <1394478649-9453-2-git-send-email-peter.maydell@linaro.org>
On Mon, Mar 10, 2014 at 07:10:37PM +0000, Peter Maydell wrote:
> Add 'U' suffixes where necessary to avoid (1 << 31) which
> shifts left into the sign bit, which is undefined behaviour.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
While not required for correctness,
I think it would be cleaner to change them all to 1U, for consistency.
> ---
> target-i386/cpu.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 0014acc..064f987 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -202,7 +202,7 @@
> #define CR0_NE_MASK (1 << 5)
> #define CR0_WP_MASK (1 << 16)
> #define CR0_AM_MASK (1 << 18)
> -#define CR0_PG_MASK (1 << 31)
> +#define CR0_PG_MASK (1U << 31)
>
> #define CR4_VME_MASK (1 << 0)
> #define CR4_PVI_MASK (1 << 1)
> @@ -436,7 +436,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_HT (1 << 28)
> #define CPUID_TM (1 << 29)
> #define CPUID_IA64 (1 << 30)
> -#define CPUID_PBE (1 << 31)
> +#define CPUID_PBE (1U << 31)
>
> #define CPUID_EXT_SSE3 (1 << 0)
> #define CPUID_EXT_PCLMULQDQ (1 << 1)
> @@ -467,7 +467,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_EXT_AVX (1 << 28)
> #define CPUID_EXT_F16C (1 << 29)
> #define CPUID_EXT_RDRAND (1 << 30)
> -#define CPUID_EXT_HYPERVISOR (1 << 31)
> +#define CPUID_EXT_HYPERVISOR (1U << 31)
>
> #define CPUID_EXT2_FPU (1 << 0)
> #define CPUID_EXT2_VME (1 << 1)
> @@ -496,7 +496,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_EXT2_RDTSCP (1 << 27)
> #define CPUID_EXT2_LM (1 << 29)
> #define CPUID_EXT2_3DNOWEXT (1 << 30)
> -#define CPUID_EXT2_3DNOW (1 << 31)
> +#define CPUID_EXT2_3DNOW (1U << 31)
>
> /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
> #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
> --
> 1.9.0
>
WARNING: multiple messages have this Message-ID (diff)
From: "Michael S. Tsirkin" <mst@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-trivial@nongnu.org, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 01/12] target-i386: Avoid shifting left into sign bit
Date: Mon, 10 Mar 2014 23:57:38 +0200 [thread overview]
Message-ID: <20140310215738.GC7104@redhat.com> (raw)
In-Reply-To: <1394478649-9453-2-git-send-email-peter.maydell@linaro.org>
On Mon, Mar 10, 2014 at 07:10:37PM +0000, Peter Maydell wrote:
> Add 'U' suffixes where necessary to avoid (1 << 31) which
> shifts left into the sign bit, which is undefined behaviour.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
While not required for correctness,
I think it would be cleaner to change them all to 1U, for consistency.
> ---
> target-i386/cpu.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 0014acc..064f987 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -202,7 +202,7 @@
> #define CR0_NE_MASK (1 << 5)
> #define CR0_WP_MASK (1 << 16)
> #define CR0_AM_MASK (1 << 18)
> -#define CR0_PG_MASK (1 << 31)
> +#define CR0_PG_MASK (1U << 31)
>
> #define CR4_VME_MASK (1 << 0)
> #define CR4_PVI_MASK (1 << 1)
> @@ -436,7 +436,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_HT (1 << 28)
> #define CPUID_TM (1 << 29)
> #define CPUID_IA64 (1 << 30)
> -#define CPUID_PBE (1 << 31)
> +#define CPUID_PBE (1U << 31)
>
> #define CPUID_EXT_SSE3 (1 << 0)
> #define CPUID_EXT_PCLMULQDQ (1 << 1)
> @@ -467,7 +467,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_EXT_AVX (1 << 28)
> #define CPUID_EXT_F16C (1 << 29)
> #define CPUID_EXT_RDRAND (1 << 30)
> -#define CPUID_EXT_HYPERVISOR (1 << 31)
> +#define CPUID_EXT_HYPERVISOR (1U << 31)
>
> #define CPUID_EXT2_FPU (1 << 0)
> #define CPUID_EXT2_VME (1 << 1)
> @@ -496,7 +496,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_EXT2_RDTSCP (1 << 27)
> #define CPUID_EXT2_LM (1 << 29)
> #define CPUID_EXT2_3DNOWEXT (1 << 30)
> -#define CPUID_EXT2_3DNOW (1 << 31)
> +#define CPUID_EXT2_3DNOW (1U << 31)
>
> /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
> #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
> --
> 1.9.0
>
next prev parent reply other threads:[~2014-03-10 21:58 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-10 19:10 [Qemu-trivial] [PATCH 00/12] Avoid shifting left into sign bit Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 19:10 ` [Qemu-trivial] [PATCH 01/12] target-i386: " Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 21:57 ` Michael S. Tsirkin [this message]
2014-03-10 21:57 ` Michael S. Tsirkin
2014-03-10 19:10 ` [Qemu-trivial] [PATCH 02/12] hw/intc/apic.c: Use uint32_t for mask word in foreach_apic Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 19:39 ` [Qemu-trivial] " Stefan Weil
2014-03-10 19:39 ` Stefan Weil
2014-03-10 21:56 ` [Qemu-trivial] " Michael S. Tsirkin
2014-03-10 21:56 ` [Qemu-devel] " Michael S. Tsirkin
2014-03-10 19:10 ` [Qemu-trivial] [PATCH 03/12] hw/pci/pci_host.c: Avoid shifting left into sign bit Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 20:03 ` [Qemu-trivial] " Stefan Weil
2014-03-10 20:03 ` Stefan Weil
2014-03-10 21:46 ` [Qemu-trivial] " Michael S. Tsirkin
2014-03-10 21:46 ` Michael S. Tsirkin
2014-03-10 21:58 ` [Qemu-trivial] " Michael S. Tsirkin
2014-03-10 21:58 ` [Qemu-devel] " Michael S. Tsirkin
2014-03-10 19:10 ` [Qemu-trivial] [PATCH 04/12] hw/i386/acpi_build.c: " Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 21:56 ` [Qemu-trivial] " Michael S. Tsirkin
2014-03-10 21:56 ` [Qemu-devel] " Michael S. Tsirkin
2014-03-10 19:10 ` [Qemu-trivial] [PATCH 05/12] target-mips: " Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 19:10 ` [Qemu-trivial] [PATCH 06/12] hw/usb/hcd-ohci.c: " Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 19:10 ` [Qemu-trivial] [PATCH 07/12] hw/intc/openpic: " Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 19:10 ` [Qemu-trivial] [PATCH 08/12] hw/ppc: " Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 19:10 ` [Qemu-trivial] [PATCH 09/12] tests/libqos/pci-pc: " Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 19:10 ` [Qemu-trivial] [PATCH 10/12] hw/intc/slavio_intctl: " Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 19:10 ` [Qemu-trivial] [PATCH 11/12] hw/intc/xilinx_intc: " Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 19:10 ` [Qemu-trivial] [PATCH 12/12] hw/pci-host/apb.c: " Peter Maydell
2014-03-10 19:10 ` [Qemu-devel] " Peter Maydell
2014-03-10 21:59 ` [Qemu-trivial] " Michael S. Tsirkin
2014-03-10 21:59 ` [Qemu-devel] " Michael S. Tsirkin
2014-03-14 16:45 ` [Qemu-trivial] " Michael Tokarev
2014-03-14 16:45 ` [Qemu-devel] " Michael Tokarev
2014-03-10 22:00 ` [Qemu-trivial] [PATCH 00/12] " Michael S. Tsirkin
2014-03-10 22:00 ` [Qemu-devel] " Michael S. Tsirkin
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