From: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
To: Chew Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Cc: Mika Westerberg
<mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
Lim Lee Booi
<lee.booi.lim-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCHv2 RESEND] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value
Date: Wed, 12 Mar 2014 08:16:05 +0100 [thread overview]
Message-ID: <20140312071605.GA2756@katana> (raw)
In-Reply-To: <1394537625-27205-1-git-send-email-chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
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On Tue, Mar 11, 2014 at 07:33:45PM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
>
> On Intel BayTrail, there was case whereby the resulting fast mode
> bus speed becomes slower (~20% slower compared to expected speed)
> if using the HCNT/LCNT calculated in the core layer. Thus, this
> patch is added to allow pci glue layer to pass in optimal
> HCNT/LCNT/SDA hold time values to core layer since the core
> layer supports cofigurable HCNT/LCNT/SDA hold time values now.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Applied to for-next, thanks!
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WARNING: multiple messages have this Message-ID (diff)
From: Wolfram Sang <wsa@the-dreams.de>
To: Chew Chiau Ee <chiau.ee.chew@intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>,
Lim Lee Booi <lee.booi.lim@intel.com>,
linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCHv2 RESEND] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value
Date: Wed, 12 Mar 2014 08:16:05 +0100 [thread overview]
Message-ID: <20140312071605.GA2756@katana> (raw)
In-Reply-To: <1394537625-27205-1-git-send-email-chiau.ee.chew@intel.com>
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On Tue, Mar 11, 2014 at 07:33:45PM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
>
> On Intel BayTrail, there was case whereby the resulting fast mode
> bus speed becomes slower (~20% slower compared to expected speed)
> if using the HCNT/LCNT calculated in the core layer. Thus, this
> patch is added to allow pci glue layer to pass in optimal
> HCNT/LCNT/SDA hold time values to core layer since the core
> layer supports cofigurable HCNT/LCNT/SDA hold time values now.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Applied to for-next, thanks!
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next prev parent reply other threads:[~2014-03-12 7:16 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-11 11:33 [PATCHv2 RESEND] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value Chew Chiau Ee
2014-03-11 11:33 ` Chew Chiau Ee
[not found] ` <1394537625-27205-1-git-send-email-chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2014-03-11 3:39 ` Chew, Chiau Ee
2014-03-11 3:39 ` Chew, Chiau Ee
2014-03-11 11:11 ` Mika Westerberg
2014-03-11 11:11 ` Mika Westerberg
2014-03-12 7:16 ` Wolfram Sang [this message]
2014-03-12 7:16 ` Wolfram Sang
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