Re: [PATCH v2 5/6] drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush'

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Mar 24, 2014 at 11:00:06PM +0530, sourab.gupta@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> In Valleyview, Operational flush cannot be enabled on
> BWG A0 [Errata BWT006]

Apparently this has been busted ever since gen4. So I think either we
should disable it for all gen4+ platforms or we should trust that the
default value is 0. The default does seem to be disabled for everything,
but since there's a w/a name for it I'm not sure if we can trust that.

BDW is a bit weird since the bit has been repurposed for some GT3 thing.
Not sure what the deal is with !GT3.

> 
> v2: Corrected the code regarding the wrong usage of
> MASKED_BIT_DISABLE (Chris)
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 3 +++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b922e38..266bfa1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -972,6 +972,9 @@ enum punit_power_well {
>  #define   ECO_GATING_CX_ONLY	(1<<3)
>  #define   ECO_FLIP_DONE		(1<<0)
>  
> +#define GEN7_CACHE_MODE_0	0x07000 /* IVB+ only */
> +#define GEN7_RC_OP_FLUSH_ENABLE (1<<0)
> +
>  #define CACHE_MODE_0_GEN7	0x7000 /* IVB+ */
>  #define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
>  #define CACHE_MODE_1		0x7004 /* IVB+ */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fd68f93..c3a8554 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5068,6 +5068,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  		   _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
>  				      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>  
> +	/* WaDisable_RenderCache_OperationalFlush:vlv */
> +	I915_WRITE(GEN7_CACHE_MODE_0, _MASKED_BIT_DISABLE(GEN7_RC_OP_FLUSH_ENABLE));
> +
>  	/* WaForceL3Serialization:vlv */
>  	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
>  		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> -- 
> 1.8.5.1

-- 
Ville Syrjälä
Intel OTC