From: Daniel Vetter <daniel@ffwll.ch>
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
intel-gfx@lists.freedesktop.org, sourab.gupta@intel.com,
Akash Goel <akash.goel@intel.com>
Subject: Re: [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
Date: Tue, 27 May 2014 18:54:33 +0200 [thread overview]
Message-ID: <20140527165433.GC14841@phenom.ffwll.local> (raw)
In-Reply-To: <20140527142723.GA27337@strange.amr.corp.intel.com>
On Tue, May 27, 2014 at 03:27:23PM +0100, Damien Lespiau wrote:
> On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gupta@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> >
> > For disabling L3 clock gating we need to set bit 25 of MMIO
> > register 940c. Earlier this was being done by just writing 1
> > into bit 25 and resetting all other bits.
> > This patch modifies the routine to read-modify-write of the
> > register, so that the values of other bits are not destroyed.
> >
> > v2: Modifying the comments and the patch commit message (Chris)
> >
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
>
> Apart from the multiline comment format and the second line not aligned
> with the '(' as we usually do:
Fixed.
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
prev parent reply other threads:[~2014-05-27 16:54 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-24 17:30 [PATCH 0/6] Rendering Specific HW Workarounds for VLV sourab.gupta
2014-03-24 17:30 ` [PATCH v4 1/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' sourab.gupta
2014-03-24 17:30 ` [PATCH v4 2/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext' sourab.gupta
2014-04-08 4:41 ` Gupta, Sourab
2014-04-14 9:45 ` [PATCH v5 " sourab.gupta
2014-05-28 9:57 ` Gupta, Sourab
2014-06-05 5:44 ` Gupta, Sourab
2014-03-24 17:30 ` [PATCH v2 3/6] drm/i915: Enabling the TLB invalidate bit in GFX Mode register sourab.gupta
2014-04-01 5:01 ` Gupta, Sourab
2014-04-02 11:34 ` Ville Syrjälä
2014-04-02 11:55 ` Daniel Vetter
2014-03-24 17:30 ` [PATCH 4/6] drm/i915/vlv: Remove the enabling of VS_TIMER_DISPATCH bit in MI MODE reg sourab.gupta
2014-03-24 17:47 ` Chris Wilson
2014-03-24 17:55 ` Gupta, Sourab
2014-03-24 18:01 ` Chris Wilson
2014-03-24 18:28 ` [PATCH v2 " sourab.gupta
2014-03-25 11:33 ` Ville Syrjälä
2014-03-25 12:31 ` [PATCH v3 4/6] drm/i915: " sourab.gupta
2014-03-25 13:11 ` Ville Syrjälä
2014-03-25 15:41 ` Daniel Vetter
2014-03-24 17:30 ` [PATCH v2 5/6] drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush' sourab.gupta
2014-04-01 10:51 ` Ville Syrjälä
2014-04-03 4:42 ` [PATCH v3 " sourab.gupta
2014-04-04 11:17 ` Ville Syrjälä
2014-04-04 11:44 ` [PATCH v4 " sourab.gupta
2014-04-04 15:24 ` Chris Wilson
2014-04-04 15:35 ` Ville Syrjälä
2014-04-04 15:59 ` Chris Wilson
2014-04-04 15:59 ` Daniel Vetter
2014-03-24 17:30 ` [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv sourab.gupta
2014-03-24 17:56 ` Damien Lespiau
2014-03-25 6:52 ` Gupta, Sourab
2014-04-01 5:22 ` Gupta, Sourab
2014-04-14 10:22 ` Gupta, Sourab
2014-05-26 10:33 ` Gupta, Sourab
2014-05-27 14:27 ` Damien Lespiau
2014-05-27 16:54 ` Daniel Vetter [this message]
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