From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/5] pinctrl: sunxi: define A31 R_PIO pin functions
Date: Thu, 10 Apr 2014 14:43:42 +0200 [thread overview]
Message-ID: <20140410124342.GR28585@lukather> (raw)
In-Reply-To: <1397132747-13917-4-git-send-email-boris.brezillon@free-electrons.com>
On Thu, Apr 10, 2014 at 02:25:45PM +0200, Boris BREZILLON wrote:
> The A31 SoC provides both PL and PM pio bank through the R_PIO block.
>
> These pins all support gpio function and can bbe assigned to system
> peripherals (like TWI, P2WI, JTAG, ...)
>
> Add new compatible string to the DT bindings doc.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Boris BREZILLON
<boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: "Randy Dunlap" <rdunlap-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
"Emilio López" <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>,
"Mike Turquette"
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
"Linus Walleij"
<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
"Chen-Yu Tsai" <wens-jdAy2FN1RRM@public.gmane.org>,
"Hans de Goede"
<hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
Shuge <shuge-0TFLnhJekD6UEPyfVivIlAC/G2K4zDHf@public.gmane.org>,
kevin-0TFLnhJekD6UEPyfVivIlAC/G2K4zDHf@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
dev-3kdeTeqwOZ9EV1b7eY7vFQ@public.gmane.org
Subject: Re: [PATCH v2 3/5] pinctrl: sunxi: define A31 R_PIO pin functions
Date: Thu, 10 Apr 2014 14:43:42 +0200 [thread overview]
Message-ID: <20140410124342.GR28585@lukather> (raw)
In-Reply-To: <1397132747-13917-4-git-send-email-boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
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On Thu, Apr 10, 2014 at 02:25:45PM +0200, Boris BREZILLON wrote:
> The A31 SoC provides both PL and PM pio bank through the R_PIO block.
>
> These pins all support gpio function and can bbe assigned to system
> peripherals (like TWI, P2WI, JTAG, ...)
>
> Add new compatible string to the DT bindings doc.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Thanks!
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Boris BREZILLON <boris.brezillon@free-electrons.com>
Cc: "Randy Dunlap" <rdunlap@infradead.org>,
"Emilio López" <emilio@elopez.com.ar>,
"Mike Turquette" <mturquette@linaro.org>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Hans de Goede" <hdegoede@redhat.com>,
Shuge <shuge@allwinnertech.com>,
kevin@allwinnertech.com, devicetree@vger.kernel.org,
linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dev@linux-sunxi.org
Subject: Re: [PATCH v2 3/5] pinctrl: sunxi: define A31 R_PIO pin functions
Date: Thu, 10 Apr 2014 14:43:42 +0200 [thread overview]
Message-ID: <20140410124342.GR28585@lukather> (raw)
In-Reply-To: <1397132747-13917-4-git-send-email-boris.brezillon@free-electrons.com>
[-- Attachment #1: Type: text/plain, Size: 575 bytes --]
On Thu, Apr 10, 2014 at 02:25:45PM +0200, Boris BREZILLON wrote:
> The A31 SoC provides both PL and PM pio bank through the R_PIO block.
>
> These pins all support gpio function and can bbe assigned to system
> peripherals (like TWI, P2WI, JTAG, ...)
>
> Add new compatible string to the DT bindings doc.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2014-04-10 12:43 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-10 12:25 [PATCH v2 0/5] ARM: sunxi: add multi pin controller support Boris BREZILLON
2014-04-10 12:25 ` Boris BREZILLON
2014-04-10 12:25 ` Boris BREZILLON
2014-04-10 12:25 ` [PATCH v2 1/5] pinctrl: sunxi: add PL and PM pin definitions Boris BREZILLON
2014-04-10 12:25 ` Boris BREZILLON
2014-04-10 12:34 ` Maxime Ripard
2014-04-10 12:34 ` Maxime Ripard
2014-04-10 12:25 ` [PATCH v2 2/5] pinctrl: sunxi: support multiple pin controller Boris BREZILLON
2014-04-10 12:25 ` Boris BREZILLON
2014-04-10 12:39 ` Maxime Ripard
2014-04-10 12:39 ` Maxime Ripard
2014-04-10 12:39 ` Maxime Ripard
2014-04-10 12:25 ` [PATCH v2 3/5] pinctrl: sunxi: define A31 R_PIO pin functions Boris BREZILLON
2014-04-10 12:25 ` Boris BREZILLON
2014-04-10 12:25 ` Boris BREZILLON
2014-04-10 12:43 ` Maxime Ripard [this message]
2014-04-10 12:43 ` Maxime Ripard
2014-04-10 12:43 ` Maxime Ripard
2014-04-10 12:25 ` [PATCH v2 4/5] pinctrl: sunxi: add reset control support Boris BREZILLON
2014-04-10 12:25 ` Boris BREZILLON
2014-04-10 12:46 ` Maxime Ripard
2014-04-10 12:46 ` Maxime Ripard
2014-04-10 12:46 ` Maxime Ripard
2014-04-10 12:25 ` [PATCH v2 5/5] ARM: sunxi: update the default ARCH_NR_GPIO for sunxi arch Boris BREZILLON
2014-04-10 12:25 ` Boris BREZILLON
2014-04-10 12:47 ` Maxime Ripard
2014-04-10 12:47 ` Maxime Ripard
2014-04-10 12:47 ` Maxime Ripard
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