From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] ARM: perf: save/restore pmu registers in pm notifier
Date: Tue, 15 Apr 2014 09:47:50 +0100 [thread overview]
Message-ID: <20140415084749.GG17408@arm.com> (raw)
In-Reply-To: <1397439742-28337-1-git-send-email-zhangwm@marvell.com>
Hello,
On Mon, Apr 14, 2014 at 02:42:22AM +0100, Neil Zhang wrote:
> From: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
>
> This adds core support for saving and restoring CPU PMU registers
> for suspend/resume support i.e. deeper C-states in cpuidle terms.
> This patch adds support only to ARMv7 PMU registers save/restore.
> It needs to be extended to xscale and ARMv6 if needed.
>
> [Neil] We found that DS-5 not work on our CA7 based SoCs.
> After debuging, found PMU registers were lost because of core power down.
> Then i found Sudeep had a patch to fix it about two years ago but not in
> the mainline, just port it.
What I don't like about this patch is that we're introducing significant
overhead for SoCs that don't require save/restore of the PMU state. I'd much
rather see core power down disabled whilst the PMU is in use but, if that's
not possible, then I think we need to:
(1) Make this conditional for cores that really need it
(2) Only save/restore if the PMU is in use (even better, just save/restore
the live registers, but that's probably not worth the effort
initially).
(3) Ensure we ->reset the PMU before doing the restore
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Neil Zhang <zhangwm@marvell.com>
Cc: "linux@arm.linux.org.uk" <linux@arm.linux.org.uk>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Sudeep Holla <Sudeep.Holla@arm.com>
Subject: Re: [PATCH v2] ARM: perf: save/restore pmu registers in pm notifier
Date: Tue, 15 Apr 2014 09:47:50 +0100 [thread overview]
Message-ID: <20140415084749.GG17408@arm.com> (raw)
In-Reply-To: <1397439742-28337-1-git-send-email-zhangwm@marvell.com>
Hello,
On Mon, Apr 14, 2014 at 02:42:22AM +0100, Neil Zhang wrote:
> From: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
>
> This adds core support for saving and restoring CPU PMU registers
> for suspend/resume support i.e. deeper C-states in cpuidle terms.
> This patch adds support only to ARMv7 PMU registers save/restore.
> It needs to be extended to xscale and ARMv6 if needed.
>
> [Neil] We found that DS-5 not work on our CA7 based SoCs.
> After debuging, found PMU registers were lost because of core power down.
> Then i found Sudeep had a patch to fix it about two years ago but not in
> the mainline, just port it.
What I don't like about this patch is that we're introducing significant
overhead for SoCs that don't require save/restore of the PMU state. I'd much
rather see core power down disabled whilst the PMU is in use but, if that's
not possible, then I think we need to:
(1) Make this conditional for cores that really need it
(2) Only save/restore if the PMU is in use (even better, just save/restore
the live registers, but that's probably not worth the effort
initially).
(3) Ensure we ->reset the PMU before doing the restore
Will
next prev parent reply other threads:[~2014-04-15 8:47 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-14 1:42 [PATCH v2] ARM: perf: save/restore pmu registers in pm notifier Neil Zhang
2014-04-14 1:42 ` Neil Zhang
2014-04-15 8:47 ` Will Deacon [this message]
2014-04-15 8:47 ` Will Deacon
2014-04-15 12:37 ` Neil Zhang
2014-04-15 12:37 ` Neil Zhang
2014-04-15 12:41 ` Will Deacon
2014-04-15 12:41 ` Will Deacon
2014-04-15 12:46 ` Neil Zhang
2014-04-15 12:46 ` Neil Zhang
2014-04-15 12:49 ` Will Deacon
2014-04-15 12:49 ` Will Deacon
2014-04-15 12:53 ` Neil Zhang
2014-04-15 12:53 ` Neil Zhang
2014-04-15 13:05 ` Sudeep Holla
2014-04-15 13:05 ` Sudeep Holla
2014-04-16 2:07 ` Neil Zhang
2014-04-16 2:07 ` Neil Zhang
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