From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv3 3/3] ARM: mvebu: implement L2/PCIe deadlock workaround
Date: Thu, 15 May 2014 10:36:57 +0100 [thread overview]
Message-ID: <20140515093657.GG11117@localhost> (raw)
In-Reply-To: <1400145519-28530-4-git-send-email-thomas.petazzoni@free-electrons.com>
On Thu, May 15, 2014 at 10:18:39AM +0100, Thomas Petazzoni wrote:
> The Marvell Armada 375 and Armada 38x SOCs, which use the Cortex-A9
> CPU core, the PL310 cache and the Marvell PCIe hardware block are
> affected a L2/PCIe deadlock caused by a system erratum when hardware
> I/O coherency is used.
>
> This deadlock can be avoided by mapping the PCIe memory areas as
> strongly-ordered (note: MT_UNCACHED is strongly-ordered), and by
> removing the outer cache sync done in software. This is done in this
> patch, thanks to the new bits of infrastructure added in 'ARM: mm:
> allow sub-architectures to override PCI I/O memory type' and 'ARM: mm:
> add support for HW coherent systems in PL310' respectively.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Lior Amsalem <alior@marvell.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Russell King <linux@arm.linux.org.uk>,
Jason Cooper <jason@lakedaemon.net>,
Tawfik Bayouk <tawfik@marvell.com>, Andrew Lunn <andrew@lunn.ch>,
Will Deacon <Will.Deacon@arm.com>,
Grant Likely <grant.likely@secretlab.ca>,
Gregory Clement <gregory.clement@free-electrons.com>,
Nadav Haklai <nadavh@marvell.com>,
Rob Herring <robh+dt@kernel.org>,
Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
Albin Tonnerre <Albin.Tonnerre@arm.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCHv3 3/3] ARM: mvebu: implement L2/PCIe deadlock workaround
Date: Thu, 15 May 2014 10:36:57 +0100 [thread overview]
Message-ID: <20140515093657.GG11117@localhost> (raw)
In-Reply-To: <1400145519-28530-4-git-send-email-thomas.petazzoni@free-electrons.com>
On Thu, May 15, 2014 at 10:18:39AM +0100, Thomas Petazzoni wrote:
> The Marvell Armada 375 and Armada 38x SOCs, which use the Cortex-A9
> CPU core, the PL310 cache and the Marvell PCIe hardware block are
> affected a L2/PCIe deadlock caused by a system erratum when hardware
> I/O coherency is used.
>
> This deadlock can be avoided by mapping the PCIe memory areas as
> strongly-ordered (note: MT_UNCACHED is strongly-ordered), and by
> removing the outer cache sync done in software. This is done in this
> patch, thanks to the new bits of infrastructure added in 'ARM: mm:
> allow sub-architectures to override PCI I/O memory type' and 'ARM: mm:
> add support for HW coherent systems in PL310' respectively.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
next prev parent reply other threads:[~2014-05-15 9:36 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-15 9:18 [PATCHv3 0/3] ARM: implement workaround for Cortex-A9/PL310/PCIe deadlock Thomas Petazzoni
2014-05-15 9:18 ` Thomas Petazzoni
2014-05-15 9:18 ` [PATCHv3 1/3] ARM: mm: allow sub-architectures to override PCI I/O memory type Thomas Petazzoni
2014-05-15 9:18 ` Thomas Petazzoni
2014-05-15 13:21 ` Arnd Bergmann
2014-05-15 13:21 ` Arnd Bergmann
2014-05-15 13:51 ` Thomas Petazzoni
2014-05-15 13:51 ` Thomas Petazzoni
2014-05-15 14:29 ` Will Deacon
2014-05-15 14:29 ` Will Deacon
2014-05-15 14:32 ` Arnd Bergmann
2014-05-15 14:32 ` Arnd Bergmann
2014-05-15 15:34 ` Will Deacon
2014-05-15 15:34 ` Will Deacon
2014-05-15 15:55 ` Arnd Bergmann
2014-05-15 15:55 ` Arnd Bergmann
2014-05-16 9:53 ` Will Deacon
2014-05-16 9:53 ` Will Deacon
2014-05-19 13:19 ` Arnd Bergmann
2014-05-19 13:19 ` Arnd Bergmann
2014-05-19 14:23 ` Will Deacon
2014-05-19 14:23 ` Will Deacon
2014-05-19 16:40 ` Arnd Bergmann
2014-05-19 16:40 ` Arnd Bergmann
2014-05-19 16:50 ` Will Deacon
2014-05-19 16:50 ` Will Deacon
2014-05-19 17:04 ` Arnd Bergmann
2014-05-19 17:04 ` Arnd Bergmann
2014-05-21 5:20 ` Jason Gunthorpe
2014-05-21 5:20 ` Jason Gunthorpe
2014-05-21 8:20 ` Arnd Bergmann
2014-05-21 8:20 ` Arnd Bergmann
2014-05-15 17:53 ` Jason Gunthorpe
2014-05-15 17:53 ` Jason Gunthorpe
2014-05-16 9:57 ` Will Deacon
2014-05-16 9:57 ` Will Deacon
2014-05-16 15:33 ` Jason Gunthorpe
2014-05-16 15:33 ` Jason Gunthorpe
2014-05-15 9:18 ` [PATCHv3 2/3] ARM: mm: add support for HW coherent systems in PL310 Thomas Petazzoni
2014-05-15 9:18 ` Thomas Petazzoni
2014-05-15 9:36 ` Catalin Marinas
2014-05-15 9:36 ` Catalin Marinas
2014-05-15 11:39 ` Thomas Petazzoni
2014-05-15 11:39 ` Thomas Petazzoni
2014-05-15 13:23 ` Arnd Bergmann
2014-05-15 13:23 ` Arnd Bergmann
2014-05-15 13:35 ` Rob Herring
2014-05-15 13:35 ` Rob Herring
2014-05-15 13:46 ` Thomas Petazzoni
2014-05-15 13:46 ` Thomas Petazzoni
2014-05-15 9:18 ` [PATCHv3 3/3] ARM: mvebu: implement L2/PCIe deadlock workaround Thomas Petazzoni
2014-05-15 9:18 ` Thomas Petazzoni
2014-05-15 9:36 ` Catalin Marinas [this message]
2014-05-15 9:36 ` Catalin Marinas
2014-05-15 13:21 ` Jason Cooper
2014-05-15 13:21 ` Jason Cooper
2014-05-15 13:50 ` Thomas Petazzoni
2014-05-15 13:50 ` Thomas Petazzoni
2014-05-15 15:31 ` Jason Cooper
2014-05-15 15:31 ` Jason Cooper
2014-05-16 7:19 ` Thomas Petazzoni
2014-05-16 7:19 ` Thomas Petazzoni
2014-05-15 13:26 ` Arnd Bergmann
2014-05-15 13:26 ` Arnd Bergmann
2014-05-15 14:22 ` Thomas Petazzoni
2014-05-15 14:22 ` Thomas Petazzoni
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