From: "Antoine Ténart" <antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Sebastian Hesselbarth
<sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: "Antoine Ténart"
<antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
kishon-l0cyMroinI0@public.gmane.org,
alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org,
zmxu-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org,
jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v4 1/7] phy: add a driver for the Berlin SATA PHY
Date: Tue, 20 May 2014 11:15:10 +0200 [thread overview]
Message-ID: <20140520091510.GA25381@kwain> (raw)
In-Reply-To: <537B1C35.20107-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Tue, May 20, 2014 at 11:11:17AM +0200, Sebastian Hesselbarth wrote:
> On 05/20/2014 11:04 AM, Antoine Ténart wrote:
> >+#define HOST_VSA_ADDR 0x0
> >+#define HOST_VSA_DATA 0x4
> >+#define PORT_VSR_ADDR 0x78
> >+#define PORT_VSR_DATA 0x7c
>
> Above two lines are indented with spaces.
Indeed ... sorry for that.
> >+#define PORT_SCR_CTL 0x2c
> >+
> >+#define CONTROL_REGISTER 0x0
> >+#define MBUS_SIZE_CONTROL 0x4
> >+
> >+#define POWER_DOWN_PHY0 BIT(6)
> >+#define POWER_DOWN_PHY1 BIT(14)
> >+#define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16)
> >+#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
> >+
> >+#define PHY_BASE 0x200
>
> ditto.
>
> >+
> >+/* register 0x01 */
> >+#define REF_FREF_SEL_25 BIT(0)
> >+#define PHY_MODE_SATA (0x0 << 5)
>
> ditto.
>
> >+
> >+/* register 0x02 */
> >+#define USE_MAX_PLL_RATE BIT(12)
>
> ditto.
>
> >+
> >+/* register 0x23 */
> >+#define DATA_BIT_WIDTH_10 (0x0 << 10)
> >+#define DATA_BIT_WIDTH_20 (0x1 << 10)
> >+#define DATA_BIT_WIDTH_40 (0x2 << 10)
>
> ditto.
>
> >+
> >+/* register 0x25 */
> >+#define PHY_GEN_MAX_1_5 (0x0 << 10)
> >+#define PHY_GEN_MAX_3_0 (0x1 << 10)
> >+#define PHY_GEN_MAX_6_0 (0x2 << 10)
>
> ditto.
Antoine
--
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
--
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WARNING: multiple messages have this Message-ID (diff)
From: antoine.tenart@free-electrons.com (Antoine Ténart)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 1/7] phy: add a driver for the Berlin SATA PHY
Date: Tue, 20 May 2014 11:15:10 +0200 [thread overview]
Message-ID: <20140520091510.GA25381@kwain> (raw)
In-Reply-To: <537B1C35.20107@gmail.com>
On Tue, May 20, 2014 at 11:11:17AM +0200, Sebastian Hesselbarth wrote:
> On 05/20/2014 11:04 AM, Antoine T?nart wrote:
> >+#define HOST_VSA_ADDR 0x0
> >+#define HOST_VSA_DATA 0x4
> >+#define PORT_VSR_ADDR 0x78
> >+#define PORT_VSR_DATA 0x7c
>
> Above two lines are indented with spaces.
Indeed ... sorry for that.
> >+#define PORT_SCR_CTL 0x2c
> >+
> >+#define CONTROL_REGISTER 0x0
> >+#define MBUS_SIZE_CONTROL 0x4
> >+
> >+#define POWER_DOWN_PHY0 BIT(6)
> >+#define POWER_DOWN_PHY1 BIT(14)
> >+#define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16)
> >+#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
> >+
> >+#define PHY_BASE 0x200
>
> ditto.
>
> >+
> >+/* register 0x01 */
> >+#define REF_FREF_SEL_25 BIT(0)
> >+#define PHY_MODE_SATA (0x0 << 5)
>
> ditto.
>
> >+
> >+/* register 0x02 */
> >+#define USE_MAX_PLL_RATE BIT(12)
>
> ditto.
>
> >+
> >+/* register 0x23 */
> >+#define DATA_BIT_WIDTH_10 (0x0 << 10)
> >+#define DATA_BIT_WIDTH_20 (0x1 << 10)
> >+#define DATA_BIT_WIDTH_40 (0x2 << 10)
>
> ditto.
>
> >+
> >+/* register 0x25 */
> >+#define PHY_GEN_MAX_1_5 (0x0 << 10)
> >+#define PHY_GEN_MAX_3_0 (0x1 << 10)
> >+#define PHY_GEN_MAX_6_0 (0x2 << 10)
>
> ditto.
Antoine
--
Antoine T?nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
WARNING: multiple messages have this Message-ID (diff)
From: "Antoine Ténart" <antoine.tenart@free-electrons.com>
To: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: "Antoine Ténart" <antoine.tenart@free-electrons.com>,
tj@kernel.org, kishon@ti.com,
alexandre.belloni@free-electrons.com,
thomas.petazzoni@free-electrons.com, zmxu@marvell.com,
jszhang@marvell.com, linux-arm-kernel@lists.infradead.org,
linux-ide@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 1/7] phy: add a driver for the Berlin SATA PHY
Date: Tue, 20 May 2014 11:15:10 +0200 [thread overview]
Message-ID: <20140520091510.GA25381@kwain> (raw)
In-Reply-To: <537B1C35.20107@gmail.com>
On Tue, May 20, 2014 at 11:11:17AM +0200, Sebastian Hesselbarth wrote:
> On 05/20/2014 11:04 AM, Antoine Ténart wrote:
> >+#define HOST_VSA_ADDR 0x0
> >+#define HOST_VSA_DATA 0x4
> >+#define PORT_VSR_ADDR 0x78
> >+#define PORT_VSR_DATA 0x7c
>
> Above two lines are indented with spaces.
Indeed ... sorry for that.
> >+#define PORT_SCR_CTL 0x2c
> >+
> >+#define CONTROL_REGISTER 0x0
> >+#define MBUS_SIZE_CONTROL 0x4
> >+
> >+#define POWER_DOWN_PHY0 BIT(6)
> >+#define POWER_DOWN_PHY1 BIT(14)
> >+#define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16)
> >+#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
> >+
> >+#define PHY_BASE 0x200
>
> ditto.
>
> >+
> >+/* register 0x01 */
> >+#define REF_FREF_SEL_25 BIT(0)
> >+#define PHY_MODE_SATA (0x0 << 5)
>
> ditto.
>
> >+
> >+/* register 0x02 */
> >+#define USE_MAX_PLL_RATE BIT(12)
>
> ditto.
>
> >+
> >+/* register 0x23 */
> >+#define DATA_BIT_WIDTH_10 (0x0 << 10)
> >+#define DATA_BIT_WIDTH_20 (0x1 << 10)
> >+#define DATA_BIT_WIDTH_40 (0x2 << 10)
>
> ditto.
>
> >+
> >+/* register 0x25 */
> >+#define PHY_GEN_MAX_1_5 (0x0 << 10)
> >+#define PHY_GEN_MAX_3_0 (0x1 << 10)
> >+#define PHY_GEN_MAX_6_0 (0x2 << 10)
>
> ditto.
Antoine
--
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
next prev parent reply other threads:[~2014-05-20 9:15 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-20 9:04 [PATCH v4 0/7] ARM: berlin: add AHCI support Antoine Ténart
2014-05-20 9:04 ` Antoine Ténart
2014-05-20 9:04 ` [PATCH v4 1/7] phy: add a driver for the Berlin SATA PHY Antoine Ténart
2014-05-20 9:04 ` Antoine Ténart
2014-05-20 9:04 ` Antoine Ténart
2014-05-20 9:11 ` Sebastian Hesselbarth
2014-05-20 9:11 ` Sebastian Hesselbarth
2014-05-20 9:11 ` Sebastian Hesselbarth
[not found] ` <537B1C35.20107-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-05-20 9:15 ` Antoine Ténart [this message]
2014-05-20 9:15 ` Antoine Ténart
2014-05-20 9:15 ` Antoine Ténart
2014-05-20 12:34 ` Bartlomiej Zolnierkiewicz
2014-05-20 12:34 ` Bartlomiej Zolnierkiewicz
2014-05-20 13:49 ` Andrew Lunn
2014-05-20 13:49 ` Andrew Lunn
2014-05-20 14:03 ` Antoine Ténart
2014-05-20 14:03 ` Antoine Ténart
2014-05-20 14:06 ` Andrew Lunn
2014-05-20 14:06 ` Andrew Lunn
2014-05-20 14:40 ` Antoine Ténart
2014-05-20 14:40 ` Antoine Ténart
2014-05-20 14:06 ` Antoine Ténart
2014-05-20 14:06 ` Antoine Ténart
2014-05-20 14:40 ` Antoine Ténart
2014-05-20 14:40 ` Antoine Ténart
2014-05-20 14:40 ` Antoine Ténart
2014-05-20 9:04 ` [PATCH v4 2/7] Documentation: bindings: add " Antoine Ténart
2014-05-20 9:04 ` Antoine Ténart
2014-05-20 9:04 ` Antoine Ténart
2014-05-20 9:04 ` [PATCH v4 3/7] ata: libahci: allow to use multiple PHYs Antoine Ténart
2014-05-20 9:04 ` Antoine Ténart
2014-05-20 9:04 ` [PATCH v4 4/7] ata: ahci_platform: add the Marvell Berlin AHCI compatible Antoine Ténart
2014-05-20 9:04 ` Antoine Ténart
2014-05-20 9:04 ` Antoine Ténart
2014-05-20 9:18 ` Sebastian Hesselbarth
2014-05-20 9:18 ` Sebastian Hesselbarth
2014-05-20 9:18 ` Sebastian Hesselbarth
2014-05-20 9:23 ` Antoine Ténart
2014-05-20 9:23 ` Antoine Ténart
[not found] ` <1400576675-25265-1-git-send-email-antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-05-20 9:04 ` [PATCH v4 5/7] Documentation: bindings: document the sub-nodes AHCI bindings Antoine Ténart
2014-05-20 9:04 ` Antoine Ténart
2014-05-20 9:04 ` Antoine Ténart
2014-05-20 9:04 ` [PATCH v4 6/7] ARM: berlin: add the AHCI node for the BG2Q Antoine Ténart
2014-05-20 9:04 ` Antoine Ténart
2014-05-20 9:04 ` [PATCH v4 7/7] ARM: berlin: enable the eSATA interface on the BG2Q DMP Antoine Ténart
2014-05-20 9:04 ` Antoine Ténart
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