i915 power management documentation

i915 power management documentation

[Gábor Bereczki]

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Hello DRM developers,

I am looking after some documentation of the performance management of the
GPU hardware, like registers

#define
GEN6_RPNSWREQ                                                         0xA008

#define GEN6_RP_CONTROL
0xA024



and the likes.



I have checked Intel documentation online, but could not find any reference
to those registers. As I understand they are in the graphics MMIO space,
but could not find any specs for these registers.

Your help is really appreciated.

BR,



Gabor Bereczki

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Re: i915 power management documentation

[Daniel Vetter]

On Mon, Jun 02, 2014 at 04:15:11PM +0200, Gábor Bereczki wrote:
> Hello DRM developers,
> 
> I am looking after some documentation of the performance management of the
> GPU hardware, like registers
> 
> #define
> GEN6_RPNSWREQ                                                         0xA008
> 
> #define GEN6_RP_CONTROL
> 0xA024
> 
> 
> 
> and the likes.
> 
> 
> 
> I have checked Intel documentation online, but could not find any reference
> to those registers. As I understand they are in the graphics MMIO space,
> but could not find any specs for these registers.

The hw guys don't yet allow us to publish docs for this. We're working on
it. For now your best guess is to look at the code or ask around on the
#intel-gfx irc channel.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: i915 power management documentation

[Sylvain BERTRAND]

On Mon, Jun 02, 2014 at 06:45:59PM +0200, Daniel Vetter wrote:
> The hw guys don't yet allow us to publish docs for this. We're working on
> it. For now your best guess is to look at the code or ask around on the
> #intel-gfx irc channel.

Fear of US patent trolls?

regards,

-- 
Sylvain

Re: i915 power management documentation

[Gábor Bereczki]

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thanks. Same with INSTDONE registers?
GEN7 seems to have 4 x 32 bit INSTDONE registers, but not even intel gpu
tools can decode them. Coudnt find anything in the registers reference docs.
BR,

Gabor


2014-06-02 19:02 GMT+02:00 Sylvain BERTRAND <sylware@legeek.net>:

> On Mon, Jun 02, 2014 at 06:45:59PM +0200, Daniel Vetter wrote:
> > The hw guys don't yet allow us to publish docs for this. We're working on
> > it. For now your best guess is to look at the code or ask around on the
> > #intel-gfx irc channel.
>
> Fear of US patent trolls?
>
> regards,
>
> --
> Sylvain
>

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