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diff for duplicates of <20140612181503.06562a38@xhacker>

diff --git a/a/1.txt b/N1/1.txt
index 695003a..455de0b 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,7 +1,7 @@
 Hi Russell,
 
 On Thu, 12 Jun 2014 02:44:23 -0700
-Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:
+Russell King - ARM Linux <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:
 
 > On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
 > > For all BG2Q SoCs, 2 cycles is the best/correct value
@@ -16,3 +16,7 @@ dirty-latency value.
 
 Thanks,
 Jisheng
+--
+To unsubscribe from this list: send the line "unsubscribe devicetree" in
+the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
diff --git a/a/content_digest b/N1/content_digest
index 9cad8c3..dbb28bc 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,15 +1,27 @@
  "ref\01402565920-5636-1-git-send-email-jszhang@marvell.com\0"
  "ref\020140612094423.GC23430@n2100.arm.linux.org.uk\0"
- "From\0jszhang@marvell.com (Jisheng Zhang)\0"
- "Subject\0[PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles\0"
+ "ref\020140612094423.GC23430-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org\0"
+ "From\0Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>\0"
+ "Subject\0Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles\0"
  "Date\0Thu, 12 Jun 2014 18:15:03 +0800\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Russell King - ARM Linux <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>\0"
+ "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>"
+  pawel.moll-5wv7dgnIgG8@public.gmane.org <pawel.moll-5wv7dgnIgG8@public.gmane.org>
+  mark.rutland-5wv7dgnIgG8@public.gmane.org <mark.rutland-5wv7dgnIgG8@public.gmane.org>
+  ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
+  galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
+  sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+  alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+  antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org <antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+  devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
+  linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
+ " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>\0"
  "\00:1\0"
  "b\0"
  "Hi Russell,\n"
  "\n"
  "On Thu, 12 Jun 2014 02:44:23 -0700\n"
- "Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:\n"
+ "Russell King - ARM Linux <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:\n"
  "\n"
  "> On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:\n"
  "> > For all BG2Q SoCs, 2 cycles is the best/correct value\n"
@@ -23,6 +35,10 @@
  "dirty-latency value.\n"
  "\n"
  "Thanks,\n"
- Jisheng
+ "Jisheng\n"
+ "--\n"
+ "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n"
+ "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n"
+ More majordomo info at  http://vger.kernel.org/majordomo-info.html
 
-0bc4f1b1986f088e6dbf610aabfa7c8ce9f698472ec4ea302eaff7d6469d9c49
+267a0b2114fac7224521c86abae7cf4a3bba0616168e312c6b124b35e77fe988

diff --git a/a/content_digest b/N2/content_digest
index 9cad8c3..e819fe7 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -1,9 +1,20 @@
  "ref\01402565920-5636-1-git-send-email-jszhang@marvell.com\0"
  "ref\020140612094423.GC23430@n2100.arm.linux.org.uk\0"
- "From\0jszhang@marvell.com (Jisheng Zhang)\0"
- "Subject\0[PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles\0"
+ "From\0Jisheng Zhang <jszhang@marvell.com>\0"
+ "Subject\0Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles\0"
  "Date\0Thu, 12 Jun 2014 18:15:03 +0800\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Russell King - ARM Linux <linux@arm.linux.org.uk>\0"
+ "Cc\0robh+dt@kernel.org <robh+dt@kernel.org>"
+  pawel.moll@arm.com <pawel.moll@arm.com>
+  mark.rutland@arm.com <mark.rutland@arm.com>
+  ijc+devicetree@hellion.org.uk <ijc+devicetree@hellion.org.uk>
+  galak@codeaurora.org <galak@codeaurora.org>
+  sebastian.hesselbarth@gmail.com <sebastian.hesselbarth@gmail.com>
+  alexandre.belloni@free-electrons.com <alexandre.belloni@free-electrons.com>
+  antoine.tenart@free-electrons.com <antoine.tenart@free-electrons.com>
+  devicetree@vger.kernel.org <devicetree@vger.kernel.org>
+  linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>
+ " linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>\0"
  "\00:1\0"
  "b\0"
  "Hi Russell,\n"
@@ -25,4 +36,4 @@
  "Thanks,\n"
  Jisheng
 
-0bc4f1b1986f088e6dbf610aabfa7c8ce9f698472ec4ea302eaff7d6469d9c49
+f048d79e7016b5b1ce31adf6b93f0899af2e512159eeb0c3a21158b938a391ba

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