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From: jszhang@marvell.com (Jisheng Zhang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
Date: Thu, 12 Jun 2014 18:15:03 +0800	[thread overview]
Message-ID: <20140612181503.06562a38@xhacker> (raw)
In-Reply-To: <20140612094423.GC23430@n2100.arm.linux.org.uk>

Hi Russell,

On Thu, 12 Jun 2014 02:44:23 -0700
Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:

> On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> > For all BG2Q SoCs, 2 cycles is the best/correct value
> 
> It would be a good idea to set all these parameters if you need to set
> them at all - in other words, setting arm,dirty-latency as well, as
> that's all part of the timing specification.
> 

Thanks for reviewing this patch. I will check with SoC people to find the correct
dirty-latency value.

Thanks,
Jisheng

WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
To: Russell King - ARM Linux <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
Cc: "robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org"
	<robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	"pawel.moll-5wv7dgnIgG8@public.gmane.org"
	<pawel.moll-5wv7dgnIgG8@public.gmane.org>,
	"mark.rutland-5wv7dgnIgG8@public.gmane.org"
	<mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	"ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org"
	<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
	"galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org"
	<galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	"sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org"
	<sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	"alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org"
	<alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
	"antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org"
	<antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
	"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
Date: Thu, 12 Jun 2014 18:15:03 +0800	[thread overview]
Message-ID: <20140612181503.06562a38@xhacker> (raw)
In-Reply-To: <20140612094423.GC23430-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>

Hi Russell,

On Thu, 12 Jun 2014 02:44:23 -0700
Russell King - ARM Linux <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:

> On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> > For all BG2Q SoCs, 2 cycles is the best/correct value
> 
> It would be a good idea to set all these parameters if you need to set
> them at all - in other words, setting arm,dirty-latency as well, as
> that's all part of the timing specification.
> 

Thanks for reviewing this patch. I will check with SoC people to find the correct
dirty-latency value.

Thanks,
Jisheng
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WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@marvell.com>
To: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: "robh+dt@kernel.org" <robh+dt@kernel.org>,
	"pawel.moll@arm.com" <pawel.moll@arm.com>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"ijc+devicetree@hellion.org.uk" <ijc+devicetree@hellion.org.uk>,
	"galak@codeaurora.org" <galak@codeaurora.org>,
	"sebastian.hesselbarth@gmail.com"
	<sebastian.hesselbarth@gmail.com>,
	"alexandre.belloni@free-electrons.com" 
	<alexandre.belloni@free-electrons.com>,
	"antoine.tenart@free-electrons.com" 
	<antoine.tenart@free-electrons.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
Date: Thu, 12 Jun 2014 18:15:03 +0800	[thread overview]
Message-ID: <20140612181503.06562a38@xhacker> (raw)
In-Reply-To: <20140612094423.GC23430@n2100.arm.linux.org.uk>

Hi Russell,

On Thu, 12 Jun 2014 02:44:23 -0700
Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:

> On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> > For all BG2Q SoCs, 2 cycles is the best/correct value
> 
> It would be a good idea to set all these parameters if you need to set
> them at all - in other words, setting arm,dirty-latency as well, as
> that's all part of the timing specification.
> 

Thanks for reviewing this patch. I will check with SoC people to find the correct
dirty-latency value.

Thanks,
Jisheng

  reply	other threads:[~2014-06-12 10:15 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-12  9:38 [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles Jisheng Zhang
2014-06-12  9:38 ` Jisheng Zhang
2014-06-12  9:38 ` Jisheng Zhang
2014-06-12  9:44 ` Russell King - ARM Linux
2014-06-12  9:44   ` Russell King - ARM Linux
2014-06-12 10:15   ` Jisheng Zhang [this message]
2014-06-12 10:15     ` Jisheng Zhang
2014-06-12 10:15     ` Jisheng Zhang
2014-06-12 10:19     ` Jisheng Zhang
2014-06-12 10:19       ` Jisheng Zhang
2014-06-12 10:19       ` Jisheng Zhang
2014-06-16 11:24 ` Sebastian Hesselbarth
2014-06-16 11:24   ` Sebastian Hesselbarth

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