From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH RFCv3 08/14] arm64: introduce aarch64_insn_gen_movewide()
Date: Fri, 18 Jul 2014 09:43:20 +0100 [thread overview]
Message-ID: <20140718084320.GB9548@arm.com> (raw)
In-Reply-To: <CABg9mcv4t_BwcaM0qgLivDBDGEfH0FwfTAR2QjJc4+i=M58cng@mail.gmail.com>
On Fri, Jul 18, 2014 at 06:47:22AM +0100, Z Lim wrote:
> (resending this email in case the first one got caught in your spam
> filter. sorry.)
>
> On Thu, Jul 17, 2014 at 10:41:02AM +0100, Will Deacon wrote:
> > On Wed, Jul 16, 2014 at 11:04:22PM +0100, Zi Shen Lim wrote:
> > > On Wed, Jul 16, 2014 at 05:17:15PM +0100, Will Deacon wrote:
> > > > On Tue, Jul 15, 2014 at 07:25:06AM +0100, Zi Shen Lim wrote:
> > > > > Introduce function to generate move wide (immediate) instructions.
> [...]
> > > > > + switch (variant) {
> > > > > + case AARCH64_INSN_VARIANT_32BIT:
> > > > > + BUG_ON(shift != 0 && shift != 16);
> > > > > + break;
> > > > > + case AARCH64_INSN_VARIANT_64BIT:
> > > > > + insn |= BIT(31);
> > > > > + BUG_ON(shift != 0 && shift != 16 && shift != 32 &&
> > > > > + shift != 48);
> > > >
> > > > Would be neater as a nested switch, perhaps? If you reorder the
> > > > outer-switch, you could probably fall-through too and combine the shift
> > > > checks.
> > >
> > > Not sure I picture what you had in mind... I couldn't come up with a
> > > neater version with the properties you described.
> > >
> > > The alternative I had was using masks instead of integer values, but
> > > one could argue that while neater, it could also be harder to read:
> > >
> > > switch (variant) {
> > > case AARCH64_INSN_VARIANT_32BIT:
> > > BUG_ON(shift & ~BIT(4));
> > > break;
> > > case AARCH64_INSN_VARIANT_64BIT:
> > > insn |= BIT(31);
> > > BUG_ON(shift & ~GENMASK(5, 4));
> > > ...
> >
> > I was thinking of using nested switches, but that doesn't fall out like I
> > hoped. How about:
> >
> > switch (variant) {
> > case AARCH64_INSN_VARIANT_64BIT:
> > BUG_ON(shift != 32 && shift != 48);
>
> Sorry this won't work. For example, on the valid case of shift==0,
> we'll barf right here - no fallthrough.
>
> Shall we just leave the code as is? :)
Yeah, I'm an idiot ;)
Cheers,
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Z Lim <zlim.lnx@gmail.com>
Cc: Catalin Marinas <Catalin.Marinas@arm.com>,
Jiang Liu <liuj97@gmail.com>,
AKASHI Takahiro <takahiro.akashi@linaro.org>,
"David S. Miller" <davem@davemloft.net>,
Daniel Borkmann <dborkman@redhat.com>,
Alexei Starovoitov <ast@plumgrid.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>
Subject: Re: [PATCH RFCv3 08/14] arm64: introduce aarch64_insn_gen_movewide()
Date: Fri, 18 Jul 2014 09:43:20 +0100 [thread overview]
Message-ID: <20140718084320.GB9548@arm.com> (raw)
In-Reply-To: <CABg9mcv4t_BwcaM0qgLivDBDGEfH0FwfTAR2QjJc4+i=M58cng@mail.gmail.com>
On Fri, Jul 18, 2014 at 06:47:22AM +0100, Z Lim wrote:
> (resending this email in case the first one got caught in your spam
> filter. sorry.)
>
> On Thu, Jul 17, 2014 at 10:41:02AM +0100, Will Deacon wrote:
> > On Wed, Jul 16, 2014 at 11:04:22PM +0100, Zi Shen Lim wrote:
> > > On Wed, Jul 16, 2014 at 05:17:15PM +0100, Will Deacon wrote:
> > > > On Tue, Jul 15, 2014 at 07:25:06AM +0100, Zi Shen Lim wrote:
> > > > > Introduce function to generate move wide (immediate) instructions.
> [...]
> > > > > + switch (variant) {
> > > > > + case AARCH64_INSN_VARIANT_32BIT:
> > > > > + BUG_ON(shift != 0 && shift != 16);
> > > > > + break;
> > > > > + case AARCH64_INSN_VARIANT_64BIT:
> > > > > + insn |= BIT(31);
> > > > > + BUG_ON(shift != 0 && shift != 16 && shift != 32 &&
> > > > > + shift != 48);
> > > >
> > > > Would be neater as a nested switch, perhaps? If you reorder the
> > > > outer-switch, you could probably fall-through too and combine the shift
> > > > checks.
> > >
> > > Not sure I picture what you had in mind... I couldn't come up with a
> > > neater version with the properties you described.
> > >
> > > The alternative I had was using masks instead of integer values, but
> > > one could argue that while neater, it could also be harder to read:
> > >
> > > switch (variant) {
> > > case AARCH64_INSN_VARIANT_32BIT:
> > > BUG_ON(shift & ~BIT(4));
> > > break;
> > > case AARCH64_INSN_VARIANT_64BIT:
> > > insn |= BIT(31);
> > > BUG_ON(shift & ~GENMASK(5, 4));
> > > ...
> >
> > I was thinking of using nested switches, but that doesn't fall out like I
> > hoped. How about:
> >
> > switch (variant) {
> > case AARCH64_INSN_VARIANT_64BIT:
> > BUG_ON(shift != 32 && shift != 48);
>
> Sorry this won't work. For example, on the valid case of shift==0,
> we'll barf right here - no fallthrough.
>
> Shall we just leave the code as is? :)
Yeah, I'm an idiot ;)
Cheers,
Will
next prev parent reply other threads:[~2014-07-18 8:43 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-15 6:24 [PATCH RFCv3 00/14] arm64: eBPF JIT compiler Zi Shen Lim
2014-07-15 6:24 ` Zi Shen Lim
2014-07-15 6:24 ` [PATCH RFCv3 01/14] arm64: introduce aarch64_insn_gen_comp_branch_imm() Zi Shen Lim
2014-07-15 6:24 ` Zi Shen Lim
2014-07-16 16:04 ` Will Deacon
2014-07-16 16:04 ` Will Deacon
2014-07-16 21:19 ` Zi Shen Lim
2014-07-16 21:19 ` Zi Shen Lim
2014-07-17 9:19 ` Will Deacon
2014-07-17 9:19 ` Will Deacon
2014-07-17 15:59 ` Alexei Starovoitov
2014-07-17 15:59 ` Alexei Starovoitov
2014-07-17 17:25 ` Will Deacon
2014-07-17 17:25 ` Will Deacon
2014-07-17 17:25 ` Will Deacon
2014-07-18 5:44 ` Z Lim
2014-07-18 5:44 ` Z Lim
2014-07-15 6:25 ` [PATCH RFCv3 02/14] arm64: introduce aarch64_insn_gen_branch_reg() Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-15 6:25 ` [PATCH RFCv3 03/14] arm64: introduce aarch64_insn_gen_cond_branch_imm() Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-15 6:25 ` [PATCH RFCv3 04/14] arm64: introduce aarch64_insn_gen_load_store_reg() Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-15 6:25 ` [PATCH RFCv3 05/14] arm64: introduce aarch64_insn_gen_load_store_pair() Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-15 6:25 ` [PATCH RFCv3 06/14] arm64: introduce aarch64_insn_gen_add_sub_imm() Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-15 6:25 ` [PATCH RFCv3 07/14] arm64: introduce aarch64_insn_gen_bitfield() Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-15 6:25 ` [PATCH RFCv3 08/14] arm64: introduce aarch64_insn_gen_movewide() Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-16 16:17 ` Will Deacon
2014-07-16 16:17 ` Will Deacon
2014-07-16 16:25 ` David Laight
2014-07-16 16:25 ` David Laight
2014-07-16 22:04 ` Zi Shen Lim
2014-07-16 22:04 ` Zi Shen Lim
2014-07-17 9:41 ` Will Deacon
2014-07-17 9:41 ` Will Deacon
2014-07-17 9:51 ` David Laight
2014-07-17 9:51 ` David Laight
2014-07-18 5:47 ` Z Lim
2014-07-18 5:47 ` Z Lim
2014-07-18 8:43 ` Will Deacon [this message]
2014-07-18 8:43 ` Will Deacon
2014-07-15 6:25 ` [PATCH RFCv3 09/14] arm64: introduce aarch64_insn_gen_add_sub_shifted_reg() Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-15 6:25 ` [PATCH RFCv3 10/14] arm64: introduce aarch64_insn_gen_data1() Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-15 6:25 ` [PATCH RFCv3 11/14] arm64: introduce aarch64_insn_gen_data2() Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-15 6:25 ` [PATCH RFCv3 12/14] arm64: introduce aarch64_insn_gen_data3() Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-15 6:25 ` [PATCH RFCv3 13/14] arm64: introduce aarch64_insn_gen_logical_shifted_reg() Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-15 6:25 ` [PATCH RFCv3 14/14] arm64: eBPF JIT compiler Zi Shen Lim
2014-07-15 6:25 ` Zi Shen Lim
2014-07-16 10:41 ` [PATCH RFCv3 00/14] " Will Deacon
2014-07-16 10:41 ` Will Deacon
2014-07-16 16:21 ` Will Deacon
2014-07-16 16:21 ` Will Deacon
2014-07-16 22:18 ` Zi Shen Lim
2014-07-16 22:18 ` Zi Shen Lim
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