[PATCH 13/11] arm64: Add support for 48-bit VA space with 64KB page configuration

[PATCH 13/11] arm64: Add support for 48-bit VA space with 64KB page configuration

[Jungseok Lee]

On Jul 22, 2014, at 00:09 +900 Catalin Marinas wrote:
> This patch allows support for 3 levels of page tables with 64KB page 
> configuration allowing 48-bit VA space. The pgd is no longer a full 
> PAGE_SIZE (PTRS_PER_PGD is 64) and (swapper|idmap)_pg_dir are not fully 
> populated (pgd_alloc falls back to kzalloc). 
> 
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 
> --- 

One more step :)

Are you going to post the next version of this series including [12/11]
and [13/11] or finalize the series?

In addition, could you put my gmail address in CC in coming patch or
the next version? It help me follow up the series easily.

- Jungseok Lee 

[PATCH 13/11] arm64: Add support for 48-bit VA space with 64KB page configuration

[Jungseok Lee]

On Jul 22, 2014, at 00:09 +900 Catalin Marinas wrote:
> This patch allows support for 3 levels of page tables with 64KB page 
> configuration allowing 48-bit VA space. The pgd is no longer a full 
> PAGE_SIZE (PTRS_PER_PGD is 64) and (swapper|idmap)_pg_dir are not fully 
> populated (pgd_alloc falls back to kzalloc). 
> 
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 
> --- 

One more step :)

Are you going to post the next version of this series including [12/11]
and [13/11] or finalize the series?

In addition, could you put my gmail address in CC in coming patch or
the next version? It help me follow up the series easily.

- Jungseok Lee 

[PATCH 13/11] arm64: Add support for 48-bit VA space with 64KB page configuration

[Catalin Marinas]

On Tue, Jul 22, 2014 at 04:13:27PM +0100, Jungseok Lee wrote:
> On Jul 22, 2014, at 00:09 +900 Catalin Marinas wrote:
> > This patch allows support for 3 levels of page tables with 64KB page 
> > configuration allowing 48-bit VA space. The pgd is no longer a full 
> > PAGE_SIZE (PTRS_PER_PGD is 64) and (swapper|idmap)_pg_dir are not fully 
> > populated (pgd_alloc falls back to kzalloc). 
> > 
> > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 
> > --- 
> 
> One more step :)

The last before the upcoming merging window. I also updated the
pgtable-4levels branch with the latest.

> Are you going to post the next version of this series including [12/11]
> and [13/11] or finalize the series?

I wasn't planning to post another series. It's good to get the clean-up
merged with the change that 48-bit VA now depends on BROKEN until KVM is
sorted (for 3.18).

> In addition, could you put my gmail address in CC in coming patch or
> the next version? It help me follow up the series easily.

Do you want me to add any reviewed etc. tags from you?

-- 
Catalin

[PATCH 13/11] arm64: Add support for 48-bit VA space with 64KB page configuration

[Jungseok Lee]

On Jul 23, 2014, at 12:37 AM, Catalin Marinas wrote:
> On Tue, Jul 22, 2014 at 04:13:27PM +0100, Jungseok Lee wrote:
>> On Jul 22, 2014, at 00:09 +900 Catalin Marinas wrote:
>>> This patch allows support for 3 levels of page tables with 64KB page 
>>> configuration allowing 48-bit VA space. The pgd is no longer a full 
>>> PAGE_SIZE (PTRS_PER_PGD is 64) and (swapper|idmap)_pg_dir are not fully 
>>> populated (pgd_alloc falls back to kzalloc). 
>>> 
>>> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 
>>> --- 
>> 
>> One more step :)
> 
> The last before the upcoming merging window. I also updated the
> pgtable-4levels branch with the latest.

I've checked it out. I will leave a comment ASAP if needed.

>> Are you going to post the next version of this series including [12/11]
>> and [13/11] or finalize the series?
> 
> I wasn't planning to post another series. It's good to get the clean-up
> merged with the change that 48-bit VA now depends on BROKEN until KVM is
> sorted (for 3.18).

I see.

>> In addition, could you put my gmail address in CC in coming patch or
>> the next version? It help me follow up the series easily.
> 
> Do you want me to add any reviewed etc. tags from you?

No, it's okay. What I mean is mailing thread, not tags.

- Jungseok Lee

[PATCH 13/11] arm64: Add support for 48-bit VA space with 64KB page configuration

[Jungseok Lee]

On Jul 23, 2014, at 12:37 AM, Catalin Marinas wrote:
> On Tue, Jul 22, 2014 at 04:13:27PM +0100, Jungseok Lee wrote:
>> On Jul 22, 2014, at 00:09 +900 Catalin Marinas wrote:
>>> This patch allows support for 3 levels of page tables with 64KB page 
>>> configuration allowing 48-bit VA space. The pgd is no longer a full 
>>> PAGE_SIZE (PTRS_PER_PGD is 64) and (swapper|idmap)_pg_dir are not fully 
>>> populated (pgd_alloc falls back to kzalloc). 
>>> 
>>> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 
>>> --- 
>> 
>> One more step :)
> 
> The last before the upcoming merging window. I also updated the
> pgtable-4levels branch with the latest.

I've tested the latest potable-4levels branch and 64KB + 3 Levels
works fine on model.

Tested-by: Jungseok Lee <jungseoklee85@gmail.com>

I hope that I'm not too late since this series is already in for-next/core
branch of arm64/linux.git repo. 

- Jungseok Lee

[PATCH 13/11] arm64: Add support for 48-bit VA space with 64KB page configuration

[Catalin Marinas]

On Wed, Jul 23, 2014 at 02:49:09PM +0100, Jungseok Lee wrote:
> On Jul 23, 2014, at 12:37 AM, Catalin Marinas wrote:
> > On Tue, Jul 22, 2014 at 04:13:27PM +0100, Jungseok Lee wrote:
> >> On Jul 22, 2014, at 00:09 +900 Catalin Marinas wrote:
> >>> This patch allows support for 3 levels of page tables with 64KB page 
> >>> configuration allowing 48-bit VA space. The pgd is no longer a full 
> >>> PAGE_SIZE (PTRS_PER_PGD is 64) and (swapper|idmap)_pg_dir are not fully 
> >>> populated (pgd_alloc falls back to kzalloc). 
> >>> 
> >>> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 
> >>> --- 
> >> 
> >> One more step :)
> > 
> > The last before the upcoming merging window. I also updated the
> > pgtable-4levels branch with the latest.
> 
> I've tested the latest potable-4levels branch and 64KB + 3 Levels
> works fine on model.
> 
> Tested-by: Jungseok Lee <jungseoklee85@gmail.com>

Thanks.

-- 
Catalin

[PATCH v7 00/11] arm64: Support 4 levels of translation tables

[Catalin Marinas]

Hi,

I've taken over Jungseok's 4-level page table series here:

https://lkml.kernel.org/g/000001cf6dc6$03ded0c0$0b9c7240$@samsung.com

I kept the same series numbering, so this is normally version 7. Changes
since v6:

- Additional fixes for duplicate (SWAPPER|IDMAP)_DIR_SIZE definitions
- Removed the fixmap pmd from swapper_pg_dir populated in head.S
- Several clean-ups in Jungseok's patches (annotated above my
  signed-off-by line)
- Removal of the pgtable-*level-hwdef.h files
- Converting levels config options to int ARM64_PGTABLE_LEVELS

Important change: I dropped the KVM support for 4 levels temporarily. I
plan to revive them but didn't have for v7.

You can also access the branch here:

git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64 pgtable-4levels

The branch is on top of the arm64 for-next/core branch.

Thanks.


Catalin Marinas (6):
  arm64: Remove duplicate (SWAPPER|IDMAP)_DIR_SIZE definitions
  arm64: Do not initialise the fixmap page tables in head.S
  arm64: Convert bool ARM64_x_LEVELS to int ARM64_PGTABLE_LEVELS
  arm64: Remove asm/pgtable-*level-hwdef.h files
  arm64: Clean up the initial page table creation in head.S
  arm64: Determine the vmalloc/vmemmap space at build time based on
    VA_BITS

Jungseok Lee (5):
  arm64: Use pr_* instead of printk
  arm64: Introduce VA_BITS and translation level options
  arm64: Add a description on 48-bit address space with 4KB pages
  arm64: Add 4 levels of page tables definition with 4KB pages
  arm64: mm: Implement 4 levels of translation tables

 Documentation/arm64/memory.txt                | 67 ++++++++-----------------
 arch/arm64/Kconfig                            | 51 ++++++++++++++++++-
 arch/arm64/include/asm/memory.h               |  6 +--
 arch/arm64/include/asm/page.h                 | 17 +++++--
 arch/arm64/include/asm/pgalloc.h              | 24 ++++++++-
 arch/arm64/include/asm/pgtable-2level-hwdef.h | 43 ----------------
 arch/arm64/include/asm/pgtable-3level-hwdef.h | 50 -------------------
 arch/arm64/include/asm/pgtable-4level-types.h | 71 +++++++++++++++++++++++++++
 arch/arm64/include/asm/pgtable-hwdef.h        | 42 ++++++++++++++--
 arch/arm64/include/asm/pgtable.h              | 56 ++++++++++++++++++---
 arch/arm64/include/asm/tlb.h                  | 11 ++++-
 arch/arm64/kernel/head.S                      | 52 +++++++++++++-------
 arch/arm64/kernel/traps.c                     | 13 +++--
 arch/arm64/mm/fault.c                         |  1 +
 arch/arm64/mm/init.c                          | 22 ++++++---
 arch/arm64/mm/ioremap.c                       | 30 ++++++++---
 arch/arm64/mm/mmu.c                           | 14 ++++--
 17 files changed, 363 insertions(+), 207 deletions(-)
 delete mode 100644 arch/arm64/include/asm/pgtable-2level-hwdef.h
 delete mode 100644 arch/arm64/include/asm/pgtable-3level-hwdef.h
 create mode 100644 arch/arm64/include/asm/pgtable-4level-types.h

[PATCH 13/11] arm64: Add support for 48-bit VA space with 64KB page configuration

[Catalin Marinas]

This patch allows support for 3 levels of page tables with 64KB page
configuration allowing 48-bit VA space. The pgd is no longer a full
PAGE_SIZE (PTRS_PER_PGD is 64) and (swapper|idmap)_pg_dir are not fully
populated (pgd_alloc falls back to kzalloc).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---

Some minor clean-up and 64K page configuration can use 48-bit VA space.

 Documentation/arm64/memory.txt |  8 ++++++++
 arch/arm64/Kconfig             |  2 +-
 arch/arm64/include/asm/page.h  | 16 +++++++++-------
 arch/arm64/kernel/head.S       |  6 ++++--
 4 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/Documentation/arm64/memory.txt b/Documentation/arm64/memory.txt
index 8845d0847a66..344e85cc7323 100644
--- a/Documentation/arm64/memory.txt
+++ b/Documentation/arm64/memory.txt
@@ -45,6 +45,14 @@ Start			End			Size		Use
 fffffc0000000000	ffffffffffffffff	   4TB		kernel
 
 
+AArch64 Linux memory layout with 64KB pages + 3 levels:
+
+Start			End			Size		Use
+-----------------------------------------------------------------------
+0000000000000000	0000ffffffffffff	 256TB		user
+ffff000000000000	ffffffffffffffff	 256TB		kernel
+
+
 For details of the virtual kernel memory layout please see the kernel
 booting log.
 
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 9fe62025776b..2c83f6f3019f 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -199,7 +199,6 @@ config ARM64_VA_BITS_42
 config ARM64_VA_BITS_48
 	bool "48-bit"
 	depends on !KVM
-	depends on ARM64_4K_PAGES
 
 endchoice
 
@@ -212,6 +211,7 @@ config ARM64_VA_BITS
 config ARM64_PGTABLE_LEVELS
 	int
 	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
+	default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
 	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 	default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
 
diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h
index 2502754d1921..7a3f462133b0 100644
--- a/arch/arm64/include/asm/page.h
+++ b/arch/arm64/include/asm/page.h
@@ -34,17 +34,19 @@
 /*
  * The idmap and swapper page tables need some space reserved in the kernel
  * image. Both require pgd, pud (4 levels only) and pmd tables to (section)
- * map the kernel. The swapper also maps the FDT (see __create_page_tables for
- * more information).
+ * map the kernel. With the 64K page configuration, swapper and idmap need to
+ * map to pte level. The swapper also maps the FDT (see __create_page_tables
+ * for more information).
  */
-#if CONFIG_ARM64_PGTABLE_LEVELS == 4
-#define SWAPPER_DIR_SIZE	(3 * PAGE_SIZE)
-#define IDMAP_DIR_SIZE		(3 * PAGE_SIZE)
+#ifdef CONFIG_ARM64_64K_PAGES
+#define SWAPPER_PGTABLE_LEVELS	(CONFIG_ARM64_PGTABLE_LEVELS)
 #else
-#define SWAPPER_DIR_SIZE	(2 * PAGE_SIZE)
-#define IDMAP_DIR_SIZE		(2 * PAGE_SIZE)
+#define SWAPPER_PGTABLE_LEVELS	(CONFIG_ARM64_PGTABLE_LEVELS - 1)
 #endif
 
+#define SWAPPER_DIR_SIZE	(SWAPPER_PGTABLE_LEVELS * PAGE_SIZE)
+#define IDMAP_DIR_SIZE		(SWAPPER_DIR_SIZE)
+
 #ifndef __ASSEMBLY__
 
 #include <asm/pgtable-types.h>
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index a6db505411bc..0bce493495e9 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -55,9 +55,11 @@
 #ifdef CONFIG_ARM64_64K_PAGES
 #define BLOCK_SHIFT	PAGE_SHIFT
 #define BLOCK_SIZE	PAGE_SIZE
+#define TABLE_SHIFT	PMD_SHIFT
 #else
 #define BLOCK_SHIFT	SECTION_SHIFT
 #define BLOCK_SIZE	SECTION_SIZE
+#define TABLE_SHIFT	PUD_SHIFT
 #endif
 
 #define KERNEL_START	KERNEL_RAM_VADDR
@@ -505,8 +507,8 @@ ENDPROC(__calc_phys_offset)
  */
 	.macro	create_pgd_entry, tbl, virt, tmp1, tmp2
 	create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
-#if CONFIG_ARM64_PGTABLE_LEVELS == 4
-	create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2
+#if SWAPPER_PGTABLE_LEVELS == 3
+	create_table_entry \tbl, \virt, TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
 #endif
 	.endm