Re: [PATCH v4 0/9] perf, x86: large PEBS interrupt threshold

[Ingo Molnar <mingo@kernel.org>]

* Yan, Zheng <zheng.z.yan@intel.com> wrote:

> On 07/31/2014 03:16 PM, Ingo Molnar wrote:
> > 
> > * Yan, Zheng <zheng.z.yan@intel.com> wrote:
> > 
> >> This patch series implements large PEBS interrupt threshold. For some
> >> limited cases, it can significantly reduce the sample overhead. Please
> >> read patch 6's commit message for more information.
> >>
> >> changes since v1:
> >>   - drop patch 'perf, core: Add all PMUs to pmu_idr'
> >>   - add comments for case that multiple counters overflow simultaneously
> >> changes since v2:
> >>   - rename perf_sched_cb_{enable,disable} to perf_sched_cb_user_{inc,dec} 
> >>   - use flag to indicate auto reload mechanism
> >>   - move codes that setup PEBS sample data to separate function
> >>   - output the PEBS records in batch 
> >>   - enable this for All (PEBS capable) hardware 
> >>   - more description for the multiplex
> >> changes since v3:
> >>   - ignore conflicting PEBS record
> > 
> > Please include performance measurements, 'significantly reduces sample 
> > overhead' is a totally inadequate description to judge this patch set.
> 
> patch 6 contains performance data.

I actually checked patch 6, because you referred to it in the 
description - but the performance data is actually in patch 5.

Which nicely demonstrates why such figures belong into 0/N as well.

Please also improve the desciption of the performance figures: what 
does plain/multi/delta mean, and convert into nicely digestible 
before/after performance comparison with human readable percentage 
figures.

"It got faster by 50% when XYZ" is so much nicer to read for everyone 
involved.

Thanks,

	Ingo