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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: sonika.jindal@intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Continuation of future readiness series
Date: Fri, 8 Aug 2014 14:55:10 +0300	[thread overview]
Message-ID: <20140808115510.GE4193@intel.com> (raw)
In-Reply-To: <1407497954-25230-1-git-send-email-sonika.jindal@intel.com>

On Fri, Aug 08, 2014 at 05:09:14PM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
> 
> Removing the check for HAS_PCH_SPLIT, it looks redundant here. Anyways all the
> platforms are checked separately.
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   40 ++++++++++++++++------------------
>  1 file changed, 19 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 89e0ac5..5a3e239 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12421,27 +12421,25 @@ static void intel_init_display(struct drm_device *dev)
>  		dev_priv->display.get_display_clock_speed =
>  			i830_get_display_clock_speed;
>  
> -	if (HAS_PCH_SPLIT(dev)) {
> -		if (IS_GEN5(dev)) {
> -			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
> -			dev_priv->display.write_eld = ironlake_write_eld;
> -		} else if (IS_GEN6(dev)) {
> -			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> -			dev_priv->display.write_eld = ironlake_write_eld;
> -			dev_priv->display.modeset_global_resources =
> -				snb_modeset_global_resources;
> -		} else if (IS_IVYBRIDGE(dev)) {
> -			/* FIXME: detect B0+ stepping and use auto training */
> -			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> -			dev_priv->display.write_eld = ironlake_write_eld;
> -			dev_priv->display.modeset_global_resources =
> -				ivb_modeset_global_resources;
> -		} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
> -			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> -			dev_priv->display.write_eld = haswell_write_eld;
> -			dev_priv->display.modeset_global_resources =
> -				haswell_modeset_global_resources;
> -		}
> +	if (IS_GEN5(dev)) {
> +		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
> +		dev_priv->display.write_eld = ironlake_write_eld;
> +	} else if (IS_GEN6(dev)) {
> +		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> +		dev_priv->display.write_eld = ironlake_write_eld;
> +		dev_priv->display.modeset_global_resources =
> +			snb_modeset_global_resources;
> +	} else if (IS_IVYBRIDGE(dev)) {
> +		/* FIXME: detect B0+ stepping and use auto training */
> +		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> +		dev_priv->display.write_eld = ironlake_write_eld;
> +		dev_priv->display.modeset_global_resources =
> +			ivb_modeset_global_resources;
> +	} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
> +		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> +		dev_priv->display.write_eld = haswell_write_eld;
> +		dev_priv->display.modeset_global_resources =
> +			haswell_modeset_global_resources;

Maybe shuffle these around a bit while you're at it so that the checks
would be roughly in gen order.

>  	} else if (IS_G4X(dev)) {
>  		dev_priv->display.write_eld = g4x_write_eld;
>  	} else if (IS_VALLEYVIEW(dev)) {
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

  reply	other threads:[~2014-08-08 11:57 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-08 11:39 [PATCH] drm/i915: Continuation of future readiness series sonika.jindal
2014-08-08 11:55 ` Ville Syrjälä [this message]
2014-08-08 14:15   ` Daniel Vetter
2014-08-11  3:36     ` [PATCH v2] " sonika.jindal
2014-08-11  9:27       ` Daniel Vetter

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