From: shawn.guo@freescale.com (Shawn Guo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V3 3/3] ARM: clk-imx6q: Add missing lvds and anaclk clock to the clock tree
Date: Mon, 18 Aug 2014 14:06:07 +0800 [thread overview]
Message-ID: <20140818060521.GA2114@dragon> (raw)
In-Reply-To: <20140811030935.GB13158@audiosh1>
On Mon, Aug 11, 2014 at 11:09:36AM +0800, Shengjiu Wang wrote:
> On Sat, Aug 09, 2014 at 09:58:42PM +0800, Shawn Guo wrote:
> > On Fri, Aug 08, 2014 at 03:02:49PM +0800, Shengjiu Wang wrote:
> > > @@ -176,8 +182,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
> > > * the "output_enable" bit as a gate, even though it's really just
> > > * enabling clock output.
> > > */
> > > - clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
> > > - clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
> > > + clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate2("lvds1_gate", "lvds1_sel", base + 0x160, 10);
> > > + clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate2("lvds2_gate", "lvds2_sel", base + 0x160, 11);
> >
> > I do not think you can simply change to use imx_clk_gate2() here. It's
> > designed for those CCGR gate clocks, each of which is controlled by two
> > bits.
> >
> > Shawn
> >
> As Lucas Stach's suggestion, we need to do add some method for mutually exclusive clock,
> lvds1_gate with lvds1_in, lvds2_gate with lvds2_in. I add imx_clk_gate2_exclusive() function in clk-gate2.c.
> So I change imx_clk_gate() to imx_clk_gate2() here.
> As you said, this is not good solution.
It's not just a "not good" solution but wrong and broken one. The net
result of that is if you call clk_enable() on lvds1_gate, both bit 10
and 11 will be set.
> So I need your suggestion, how can I do?
I guess we will need a new clock type to handle such mutually exclusive
clocks, rather than patching clk-gate2.
> First, is it allowable that to add imx_clk_gate2_exclusive() function, is there a more better way?
Again, this is completely wrong.
> second, or should I change the clk-gate.c to add exclusive control?
If such mutually exclusive clocks are somehow common across different
clock controllers, we can propose to change clk-gate.c for handling
them. But I'm not sure this is a common case.
Shawn
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawn.guo@freescale.com>
To: Shengjiu Wang <shengjiu.wang@freescale.com>
Cc: <kernel@pengutronix.de>, <linux@arm.linux.org.uk>,
<robh+dt@kernel.org>, <pawel.moll@arm.com>,
<mark.rutland@arm.com>, <ijc+devicetree@hellion.org.uk>,
<galak@codeaurora.org>, <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V3 3/3] ARM: clk-imx6q: Add missing lvds and anaclk clock to the clock tree
Date: Mon, 18 Aug 2014 14:06:07 +0800 [thread overview]
Message-ID: <20140818060521.GA2114@dragon> (raw)
In-Reply-To: <20140811030935.GB13158@audiosh1>
On Mon, Aug 11, 2014 at 11:09:36AM +0800, Shengjiu Wang wrote:
> On Sat, Aug 09, 2014 at 09:58:42PM +0800, Shawn Guo wrote:
> > On Fri, Aug 08, 2014 at 03:02:49PM +0800, Shengjiu Wang wrote:
> > > @@ -176,8 +182,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
> > > * the "output_enable" bit as a gate, even though it's really just
> > > * enabling clock output.
> > > */
> > > - clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
> > > - clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
> > > + clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate2("lvds1_gate", "lvds1_sel", base + 0x160, 10);
> > > + clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate2("lvds2_gate", "lvds2_sel", base + 0x160, 11);
> >
> > I do not think you can simply change to use imx_clk_gate2() here. It's
> > designed for those CCGR gate clocks, each of which is controlled by two
> > bits.
> >
> > Shawn
> >
> As Lucas Stach's suggestion, we need to do add some method for mutually exclusive clock,
> lvds1_gate with lvds1_in, lvds2_gate with lvds2_in. I add imx_clk_gate2_exclusive() function in clk-gate2.c.
> So I change imx_clk_gate() to imx_clk_gate2() here.
> As you said, this is not good solution.
It's not just a "not good" solution but wrong and broken one. The net
result of that is if you call clk_enable() on lvds1_gate, both bit 10
and 11 will be set.
> So I need your suggestion, how can I do?
I guess we will need a new clock type to handle such mutually exclusive
clocks, rather than patching clk-gate2.
> First, is it allowable that to add imx_clk_gate2_exclusive() function, is there a more better way?
Again, this is completely wrong.
> second, or should I change the clk-gate.c to add exclusive control?
If such mutually exclusive clocks are somehow common across different
clock controllers, we can propose to change clk-gate.c for handling
them. But I'm not sure this is a common case.
Shawn
next prev parent reply other threads:[~2014-08-18 6:06 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-08 7:02 [PATCH V3 0/3] refine clock tree for esai in imx6q Shengjiu Wang
2014-08-08 7:02 ` Shengjiu Wang
2014-08-08 7:02 ` [PATCH V3 1/3] ARM: clk-imx6q: refine clock tree for ESAI Shengjiu Wang
2014-08-08 7:02 ` Shengjiu Wang
2014-08-08 7:02 ` [PATCH V3 2/3] ARM: clk-gate2: Add API imx_clk_gate2_exclusive for clk_gate2 Shengjiu Wang
2014-08-08 7:02 ` Shengjiu Wang
2014-08-09 13:33 ` Shawn Guo
2014-08-09 13:33 ` Shawn Guo
2014-08-11 2:56 ` Shengjiu Wang
2014-08-11 2:56 ` Shengjiu Wang
2014-08-08 7:02 ` [PATCH V3 3/3] ARM: clk-imx6q: Add missing lvds and anaclk clock to the clock tree Shengjiu Wang
2014-08-08 7:02 ` Shengjiu Wang
2014-08-09 13:58 ` Shawn Guo
2014-08-09 13:58 ` Shawn Guo
2014-08-11 3:09 ` Shengjiu Wang
2014-08-11 3:09 ` Shengjiu Wang
2014-08-18 6:06 ` Shawn Guo [this message]
2014-08-18 6:06 ` Shawn Guo
2014-08-25 7:40 ` Shengjiu Wang
2014-08-25 7:40 ` Shengjiu Wang
2014-08-25 11:21 ` Shawn Guo
2014-08-25 11:21 ` Shawn Guo
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