Re: [PATCH 2/3] can: flexcan.c: Re-write receive path to use MB queue instead of FIFO

[David Jander <david@protonic.nl>]

On Tue, 02 Sep 2014 13:30:24 +0200
Marc Kleine-Budde <mkl@pengutronix.de> wrote:

> On 08/27/2014 11:58 AM, David Jander wrote:
> > The FlexCAN controller has a RX FIFO that is only 6 messages deep, and a
> > mailbox space capable of holding up to 63 messages.
> > This space was largely unused, limiting the permissible latency from
> > interrupt to NAPI to only 6 messages. This patch uses all available MBs
> > for message reception and frees the MBs in the IRQ handler to greatly
> > decrease the likelihood of receive overruns.
> 
> What about the order of the incoming CAN frames? Is it still preserved?
> 
> You make use of the CTRL2 register, which is not present on some older
> (but supported) flexcan IP cores. You increase FLEXCAN_MCR_MAXMB to
> 0x40, which is not supported on older IPs. The register rximr, is also
> not present on older cores. Don't break support for the older CAN cores.

I've checked the RM of i.MX53, i.MX28 and i.MX25, and they all seem to support
the rximr registers. Which IP version doesn't support them (that is still
supported by this driver anyway)?

AFAICS, the only unsupported feature on older SoC's is the CTRL2 register, and
the fact that the documentation says the MCR_MAXMB field is only 6 bits wide,
right?

Best regards,

-- 
David Jander
Protonic Holland.