* [PATCH] sparc64: T5 PMU
@ 2014-09-07 15:49 Bob Picco
2014-09-09 22:13 ` David Miller
2014-09-10 14:32 ` Bob Picco
0 siblings, 2 replies; 3+ messages in thread
From: Bob Picco @ 2014-09-07 15:49 UTC (permalink / raw)
To: sparclinux
From: bob picco <bpicco@meloft.net>
The T5 (niagara5) has different PCR related HV fast trap values and a new
HV API Group. This patch utilizes these and shares when possible with niagara4.
We use the same sparc_pmu niagara4_pmu. Should there be new effort to
obtain the MCU perf statistics then this would have to be changed.
Cc: sparclinux@vger.kernel.org
Signed-off-by: Bob Picco <bob.picco@oracle.com>
---
arch/sparc/include/asm/hypervisor.h | 11 ++++++++
arch/sparc/kernel/hvapi.c | 1 +
arch/sparc/kernel/hvcalls.S | 16 ++++++++++++
arch/sparc/kernel/pcr.c | 44 ++++++++++++++++++++++++++++++++--
arch/sparc/kernel/perf_event.c | 3 +-
5 files changed, 71 insertions(+), 4 deletions(-)
diff --git a/arch/sparc/include/asm/hypervisor.h b/arch/sparc/include/asm/hypervisor.h
index 94b39ca..4f6725f 100644
--- a/arch/sparc/include/asm/hypervisor.h
+++ b/arch/sparc/include/asm/hypervisor.h
@@ -2947,6 +2947,16 @@ unsigned long sun4v_vt_set_perfreg(unsigned long reg_num,
unsigned long reg_val);
#endif
+#define HV_FAST_T5_GET_PERFREG 0x1a8
+#define HV_FAST_T5_SET_PERFREG 0x1a9
+
+#ifndef __ASSEMBLY__
+unsigned long sun4v_t5_get_perfreg(unsigned long reg_num,
+ unsigned long *reg_val);
+unsigned long sun4v_t5_set_perfreg(unsigned long reg_num,
+ unsigned long reg_val);
+#endif
+
/* Function numbers for HV_CORE_TRAP. */
#define HV_CORE_SET_VER 0x00
#define HV_CORE_PUTCHAR 0x01
@@ -2978,6 +2988,7 @@ unsigned long sun4v_vt_set_perfreg(unsigned long reg_num,
#define HV_GRP_VF_CPU 0x0205
#define HV_GRP_KT_CPU 0x0209
#define HV_GRP_VT_CPU 0x020c
+#define HV_GRP_T5_CPU 0x0211
#define HV_GRP_DIAG 0x0300
#ifndef __ASSEMBLY__
diff --git a/arch/sparc/kernel/hvapi.c b/arch/sparc/kernel/hvapi.c
index c0a2de0..5c55145 100644
--- a/arch/sparc/kernel/hvapi.c
+++ b/arch/sparc/kernel/hvapi.c
@@ -46,6 +46,7 @@ static struct api_info api_table[] = {
{ .group = HV_GRP_VF_CPU, },
{ .group = HV_GRP_KT_CPU, },
{ .group = HV_GRP_VT_CPU, },
+ { .group = HV_GRP_T5_CPU, },
{ .group = HV_GRP_DIAG, .flags = FLAG_PRE_API },
};
diff --git a/arch/sparc/kernel/hvcalls.S b/arch/sparc/kernel/hvcalls.S
index f3ab509..caedf83 100644
--- a/arch/sparc/kernel/hvcalls.S
+++ b/arch/sparc/kernel/hvcalls.S
@@ -821,3 +821,19 @@ ENTRY(sun4v_vt_set_perfreg)
retl
nop
ENDPROC(sun4v_vt_set_perfreg)
+
+ENTRY(sun4v_t5_get_perfreg)
+ mov %o1, %o4
+ mov HV_FAST_T5_GET_PERFREG, %o5
+ ta HV_FAST_TRAP
+ stx %o1, [%o4]
+ retl
+ nop
+ENDPROC(sun4v_t5_get_perfreg)
+
+ENTRY(sun4v_t5_set_perfreg)
+ mov HV_FAST_T5_SET_PERFREG, %o5
+ ta HV_FAST_TRAP
+ retl
+ nop
+ENDPROC(sun4v_t5_set_perfreg)
diff --git a/arch/sparc/kernel/pcr.c b/arch/sparc/kernel/pcr.c
index 269af58..31b26b5 100644
--- a/arch/sparc/kernel/pcr.c
+++ b/arch/sparc/kernel/pcr.c
@@ -191,12 +191,41 @@ static const struct pcr_ops n4_pcr_ops = {
.pcr_nmi_disable = PCR_N4_PICNPT,
};
+static u64 n5_pcr_read(unsigned long reg_num)
+{
+ unsigned long val;
+
+ (void) sun4v_t5_get_perfreg(reg_num, &val);
+
+ return val;
+}
+
+static void n5_pcr_write(unsigned long reg_num, u64 val)
+{
+ (void) sun4v_t5_set_perfreg(reg_num, val);
+}
+
+static const struct pcr_ops n5_pcr_ops = {
+ .read_pcr = n5_pcr_read,
+ .write_pcr = n5_pcr_write,
+ .read_pic = n4_pic_read,
+ .write_pic = n4_pic_write,
+ .nmi_picl_value = n4_picl_value,
+ .pcr_nmi_enable = (PCR_N4_PICNPT | PCR_N4_STRACE |
+ PCR_N4_UTRACE | PCR_N4_TOE |
+ (26 << PCR_N4_SL_SHIFT)),
+ .pcr_nmi_disable = PCR_N4_PICNPT,
+};
+
+
static unsigned long perf_hsvc_group;
static unsigned long perf_hsvc_major;
static unsigned long perf_hsvc_minor;
static int __init register_perf_hsvc(void)
{
+ unsigned long hverror;
+
if (tlb_type = hypervisor) {
switch (sun4v_chip_type) {
case SUN4V_CHIP_NIAGARA1:
@@ -215,6 +244,9 @@ static int __init register_perf_hsvc(void)
perf_hsvc_group = HV_GRP_VT_CPU;
break;
+ case SUN4V_CHIP_NIAGARA5:
+ perf_hsvc_group = HV_GRP_T5_CPU;
+ break;
default:
return -ENODEV;
}
@@ -222,10 +254,12 @@ static int __init register_perf_hsvc(void)
perf_hsvc_major = 1;
perf_hsvc_minor = 0;
- if (sun4v_hvapi_register(perf_hsvc_group,
+ hverror = sun4v_hvapi_register(perf_hsvc_group,
perf_hsvc_major,
- &perf_hsvc_minor)) {
- printk("perfmon: Could not register hvapi.\n");
+ &perf_hsvc_minor);
+ if (hverror) {
+ pr_err("perfmon: Could not register hvapi(0x%lx).\n",
+ hverror);
return -ENODEV;
}
}
@@ -254,6 +288,10 @@ static int __init setup_sun4v_pcr_ops(void)
pcr_ops = &n4_pcr_ops;
break;
+ case SUN4V_CHIP_NIAGARA5:
+ pcr_ops = &n5_pcr_ops;
+ break;
+
default:
ret = -ENODEV;
break;
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index d35c490..c9759ad 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -1662,7 +1662,8 @@ static bool __init supported_pmu(void)
sparc_pmu = &niagara2_pmu;
return true;
}
- if (!strcmp(sparc_pmu_type, "niagara4")) {
+ if (!strcmp(sparc_pmu_type, "niagara4") ||
+ !strcmp(sparc_pmu_type, "niagara5")) {
sparc_pmu = &niagara4_pmu;
return true;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] sparc64: T5 PMU
2014-09-07 15:49 [PATCH] sparc64: T5 PMU Bob Picco
@ 2014-09-09 22:13 ` David Miller
2014-09-10 14:32 ` Bob Picco
1 sibling, 0 replies; 3+ messages in thread
From: David Miller @ 2014-09-09 22:13 UTC (permalink / raw)
To: sparclinux
From: Bob Picco <bpicco@meloft.net>
Date: Sun, 7 Sep 2014 11:49:49 -0400
> From: bob picco <bpicco@meloft.net>
>
> The T5 (niagara5) has different PCR related HV fast trap values and a new
> HV API Group. This patch utilizes these and shares when possible with niagara4.
>
> We use the same sparc_pmu niagara4_pmu. Should there be new effort to
> obtain the MCU perf statistics then this would have to be changed.
>
> Cc: sparclinux@vger.kernel.org
> Signed-off-by: Bob Picco <bob.picco@oracle.com>
This patch looks fine but needs some minor coding style fixups.
> +unsigned long sun4v_t5_get_perfreg(unsigned long reg_num,
> + unsigned long *reg_val);
Arguments on the second and subsequent line of a function declaration
or call need to start exactly at the first column after the openning
parenthesis of the first line. You must use the appropriate number
of TAB and SPACE characters necessary to achieve this.
> - if (sun4v_hvapi_register(perf_hsvc_group,
> + hverror = sun4v_hvapi_register(perf_hsvc_group,
> perf_hsvc_major,
Since you are changing where the openning parenthesis of this function
call is located, you have to reindent the following lines as needed.
> + pr_err("perfmon: Could not register hvapi(0x%lx).\n",
> + hverror);
Not a blocker for this patch, but we probably want an "hverr_to_string()"
helper function so that we can print these out mnenomically.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] sparc64: T5 PMU
2014-09-07 15:49 [PATCH] sparc64: T5 PMU Bob Picco
2014-09-09 22:13 ` David Miller
@ 2014-09-10 14:32 ` Bob Picco
1 sibling, 0 replies; 3+ messages in thread
From: Bob Picco @ 2014-09-10 14:32 UTC (permalink / raw)
To: sparclinux
David Miller wrote: [Tue Sep 09 2014, 06:13:48PM EDT]
> From: Bob Picco <bpicco@meloft.net>
> Date: Sun, 7 Sep 2014 11:49:49 -0400
>
> > From: bob picco <bpicco@meloft.net>
> >
> > The T5 (niagara5) has different PCR related HV fast trap values and a new
> > HV API Group. This patch utilizes these and shares when possible with niagara4.
> >
> > We use the same sparc_pmu niagara4_pmu. Should there be new effort to
> > obtain the MCU perf statistics then this would have to be changed.
> >
> > Cc: sparclinux@vger.kernel.org
> > Signed-off-by: Bob Picco <bob.picco@oracle.com>
>
> This patch looks fine but needs some minor coding style fixups.
Okay.
> > +unsigned long sun4v_t5_get_perfreg(unsigned long reg_num,
> > + unsigned long *reg_val);
>
> Arguments on the second and subsequent line of a function declaration
> or call need to start exactly at the first column after the openning
> parenthesis of the first line. You must use the appropriate number
> of TAB and SPACE characters necessary to achieve this.
My Berkeley and Bell Labs style always creeps back in. Sorry.
>
> > - if (sun4v_hvapi_register(perf_hsvc_group,
> > + hverror = sun4v_hvapi_register(perf_hsvc_group,
> > perf_hsvc_major,
>
> Since you are changing where the openning parenthesis of this function
> call is located, you have to reindent the following lines as needed.
Okay. I'll ask another person locally should my confusion remain :)
>
> > + pr_err("perfmon: Could not register hvapi(0x%lx).\n",
> > + hverror);
>
> Not a blocker for this patch, but we probably want an "hverr_to_string()"
> helper function so that we can print these out mnenomically.
I agree.
thanx for the review,
bob
> --
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2014-09-07 15:49 [PATCH] sparc64: T5 PMU Bob Picco
2014-09-09 22:13 ` David Miller
2014-09-10 14:32 ` Bob Picco
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