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From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/7] clk: sunxi: Add post clk divider for factor clocks
Date: Tue, 16 Sep 2014 17:57:11 +0200	[thread overview]
Message-ID: <20140916155711.GF2166@lukather> (raw)
In-Reply-To: <54145822.4020607@elopez.com.ar>

Hi Emilio,

On Sat, Sep 13, 2014 at 11:43:46AM -0300, Emilio L?pez wrote:
> Hi,
> 
> El 06/09/14 a las 07:47, Chen-Yu Tsai escibi?:
> >Some factor clocks, mostly PLLs, have an extra fixed divider just before
> >the clock output. Add an option to the factor clk driver config data to
> >specify this divider.
> >
> >Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >---
> >  drivers/clk/sunxi/clk-factors.c | 3 +++
> >  drivers/clk/sunxi/clk-factors.h | 1 +
> >  2 files changed, 4 insertions(+)
> >
> >diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
> >index 2057c8a..435111d 100644
> >--- a/drivers/clk/sunxi/clk-factors.c
> >+++ b/drivers/clk/sunxi/clk-factors.c
> >@@ -64,6 +64,9 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
> >  	/* Calculate the rate */
> >  	rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);
> >
> >+	if (config->post_div)
> >+		rate /= config->post_div;
> >+
> >  	return rate;
> >  }
> >
> >diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
> >index d2d0efa..ce70c65 100644
> >--- a/drivers/clk/sunxi/clk-factors.h
> >+++ b/drivers/clk/sunxi/clk-factors.h
> >@@ -16,6 +16,7 @@ struct clk_factors_config {
> >  	u8 pshift;
> >  	u8 pwidth;
> >  	u8 n_start;
> >+	u8 post_div;
> >  };
> >
> >  struct clk_factors {
> >
> 
> For the record, I liked your solution on[1] more, as it's in line
> with what we're doing on the other sunxi platforms, instead of
> adding features in factors to cover for some cases. But it's your
> and Maxime's call, as I haven't written any of the sun6i code so
> far.

No, you still wrote most of the clock support, so your opinion is
always valuable (and valued).

Thing is, unlike what was done in the sun4i driver where there was a
"real" technical issue that was preventing us from using only
fixed-factor, we're not in such a case in sun6i (and later,
apparently).

PLL6 has only one output, which is then directly multiplied by
fixed-factors, without any (pre|post)-dividers for any of them.

That means that following what you did for the sun4i would just
register 3 "dumbs" fixed-factors, that we couldn't reference from DT,
or through a cryptic index (which is not even documented in our
bindings).

I'd be fine either way, I just prefer the solution that has less code
and is more explicit.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: "Emilio López" <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
Cc: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
	Mike Turquette
	<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Vinod Koul <vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	Dan Williams
	<dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	Grant Likely
	<grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
	dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 1/7] clk: sunxi: Add post clk divider for factor clocks
Date: Tue, 16 Sep 2014 17:57:11 +0200	[thread overview]
Message-ID: <20140916155711.GF2166@lukather> (raw)
In-Reply-To: <54145822.4020607-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>

[-- Attachment #1: Type: text/plain, Size: 2564 bytes --]

Hi Emilio,

On Sat, Sep 13, 2014 at 11:43:46AM -0300, Emilio López wrote:
> Hi,
> 
> El 06/09/14 a las 07:47, Chen-Yu Tsai escibió:
> >Some factor clocks, mostly PLLs, have an extra fixed divider just before
> >the clock output. Add an option to the factor clk driver config data to
> >specify this divider.
> >
> >Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> >---
> >  drivers/clk/sunxi/clk-factors.c | 3 +++
> >  drivers/clk/sunxi/clk-factors.h | 1 +
> >  2 files changed, 4 insertions(+)
> >
> >diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
> >index 2057c8a..435111d 100644
> >--- a/drivers/clk/sunxi/clk-factors.c
> >+++ b/drivers/clk/sunxi/clk-factors.c
> >@@ -64,6 +64,9 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
> >  	/* Calculate the rate */
> >  	rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);
> >
> >+	if (config->post_div)
> >+		rate /= config->post_div;
> >+
> >  	return rate;
> >  }
> >
> >diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
> >index d2d0efa..ce70c65 100644
> >--- a/drivers/clk/sunxi/clk-factors.h
> >+++ b/drivers/clk/sunxi/clk-factors.h
> >@@ -16,6 +16,7 @@ struct clk_factors_config {
> >  	u8 pshift;
> >  	u8 pwidth;
> >  	u8 n_start;
> >+	u8 post_div;
> >  };
> >
> >  struct clk_factors {
> >
> 
> For the record, I liked your solution on[1] more, as it's in line
> with what we're doing on the other sunxi platforms, instead of
> adding features in factors to cover for some cases. But it's your
> and Maxime's call, as I haven't written any of the sun6i code so
> far.

No, you still wrote most of the clock support, so your opinion is
always valuable (and valued).

Thing is, unlike what was done in the sun4i driver where there was a
"real" technical issue that was preventing us from using only
fixed-factor, we're not in such a case in sun6i (and later,
apparently).

PLL6 has only one output, which is then directly multiplied by
fixed-factors, without any (pre|post)-dividers for any of them.

That means that following what you did for the sun4i would just
register 3 "dumbs" fixed-factors, that we couldn't reference from DT,
or through a cryptic index (which is not even documented in our
bindings).

I'd be fine either way, I just prefer the solution that has less code
and is more explicit.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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  parent reply	other threads:[~2014-09-16 15:57 UTC|newest]

Thread overview: 72+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-06 10:47 [PATCH 0/7] clk: sun6i: Unify AHB1 clock and fix rate calculation Chen-Yu Tsai
2014-09-06 10:47 ` Chen-Yu Tsai
2014-09-06 10:47 ` [PATCH 1/7] clk: sunxi: Add post clk divider for factor clocks Chen-Yu Tsai
2014-09-06 10:47   ` Chen-Yu Tsai
2014-09-11 20:36   ` Maxime Ripard
2014-09-11 20:36     ` Maxime Ripard
2014-09-13 14:43   ` Emilio López
2014-09-13 14:43     ` Emilio López
2014-09-16  8:11     ` [linux-sunxi] " Chen-Yu Tsai
2014-09-16  8:11       ` Chen-Yu Tsai
2014-09-16 15:57     ` Maxime Ripard [this message]
2014-09-16 15:57       ` Maxime Ripard
2014-09-24 15:35       ` Chen-Yu Tsai
2014-09-24 15:35         ` Chen-Yu Tsai
2014-09-27  7:07         ` Maxime Ripard
2014-09-27  7:07           ` Maxime Ripard
2014-09-27  7:23           ` Chen-Yu Tsai
2014-09-27  7:23             ` Chen-Yu Tsai
2014-09-06 10:47 ` [PATCH 2/7] clk: sunxi: Fix PLL6 calculation on sun6i Chen-Yu Tsai
2014-09-06 10:47   ` Chen-Yu Tsai
2014-09-11 20:38   ` Maxime Ripard
2014-09-11 20:38     ` Maxime Ripard
2014-09-06 10:47 ` [PATCH 3/7] clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider Chen-Yu Tsai
2014-09-06 10:47   ` Chen-Yu Tsai
2014-09-11 21:02   ` Maxime Ripard
2014-09-11 21:02     ` Maxime Ripard
2014-09-12  3:16     ` Chen-Yu Tsai
2014-09-12  3:16       ` Chen-Yu Tsai
2014-09-13 10:26       ` Maxime Ripard
2014-09-13 10:26         ` Maxime Ripard
2014-09-25 23:03         ` Mike Turquette
2014-09-25 23:03           ` Mike Turquette
2014-09-26  8:28           ` Maxime Ripard
2014-09-26  8:28             ` Maxime Ripard
2014-09-06 10:47 ` [PATCH 4/7] ARM: dts: sun8i: Unify ahb1 clock nodes Chen-Yu Tsai
2014-09-06 10:47   ` Chen-Yu Tsai
2014-09-06 10:47 ` [PATCH 5/7] ARM: dts: sun6i: " Chen-Yu Tsai
2014-09-06 10:47   ` Chen-Yu Tsai
2014-09-06 10:47 ` [PATCH 6/7] ARM: dts: sun6i: Add required ahb1 clock parent and rates for dma controller Chen-Yu Tsai
2014-09-06 10:47   ` Chen-Yu Tsai
2014-09-11 21:15   ` Maxime Ripard
2014-09-11 21:15     ` Maxime Ripard
2014-09-12  2:10     ` Chen-Yu Tsai
2014-09-12  2:10       ` Chen-Yu Tsai
2014-09-16 15:48       ` Maxime Ripard
2014-09-16 15:48         ` Maxime Ripard
2014-09-16 16:01         ` Chen-Yu Tsai
2014-09-16 16:01           ` Chen-Yu Tsai
2014-09-20  9:59           ` Maxime Ripard
2014-09-20  9:59             ` Maxime Ripard
2014-09-21  8:31             ` Chen-Yu Tsai
2014-09-21  8:31               ` Chen-Yu Tsai
2014-09-25 13:41               ` Maxime Ripard
2014-09-25 13:41                 ` Maxime Ripard
2014-09-06 10:47 ` [PATCH 7/7] dmaengine: sun6i: Remove obsolete clk muxing code Chen-Yu Tsai
2014-09-06 10:47   ` Chen-Yu Tsai
2014-09-11 21:16   ` Maxime Ripard
2014-09-11 21:16     ` Maxime Ripard
2014-09-24  5:10   ` Vinod Koul
2014-09-24  5:10     ` Vinod Koul
2014-09-11 20:36 ` [PATCH 0/7] clk: sun6i: Unify AHB1 clock and fix rate calculation Maxime Ripard
2014-09-11 20:36   ` Maxime Ripard
2014-09-26  0:25   ` Mike Turquette
2014-09-26  0:25     ` Mike Turquette
2014-09-26  0:55     ` Chen-Yu Tsai
2014-09-26  0:55       ` Chen-Yu Tsai
2014-09-26 18:53       ` Mike Turquette
2014-09-26 18:53         ` Mike Turquette
2014-10-09  3:16         ` Chen-Yu Tsai
2014-10-09  3:16           ` Chen-Yu Tsai
2014-10-13 10:39           ` Maxime Ripard
2014-10-13 10:39             ` Maxime Ripard

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