From: Thierry Reding <thierry.reding@gmail.com>
To: Sean Paul <seanpaul@chromium.org>
Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate
Date: Mon, 22 Sep 2014 12:07:47 +0200 [thread overview]
Message-ID: <20140922100746.GM1470@ulmo> (raw)
In-Reply-To: <1411156429-19797-1-git-send-email-seanpaul@chromium.org>
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On Fri, Sep 19, 2014 at 03:53:48PM -0400, Sean Paul wrote:
> Per NVidia, this clock rate should be around 70MHz in
> order to properly sample reads on data lane 0.
Can you point out where you get 70 MHz from? I only see the TRM mention
72 MHz that are needed for calibration.
Also, what's the effect of doing this? Does it fix an issue that you're
seeing?
Thierry
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next prev parent reply other threads:[~2014-09-22 10:07 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-19 19:53 [PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate Sean Paul
2014-09-19 19:53 ` [PATCH 2/2] ARM: tegra: Add lp_parent clock to dsi Sean Paul
2014-09-22 10:07 ` Thierry Reding [this message]
[not found] ` <1411156429-19797-1-git-send-email-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-09-22 7:28 ` [PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate Andrzej Hajda
2014-09-22 9:00 ` Lucas Stach
2014-09-22 10:11 ` Thierry Reding
2014-10-08 15:11 ` Peter De Schrijver
[not found] ` <20141008151155.GC4809-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2014-10-08 16:03 ` Sean Paul
2014-09-22 17:46 ` Mark Rutland
2014-09-23 7:22 ` Thierry Reding
2014-09-27 20:05 ` Mike Turquette
2014-09-29 8:17 ` Thierry Reding
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