From: Thierry Reding <thierry.reding@gmail.com>
To: Sean Paul <seanpaul@chromium.org>
Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate
Date: Mon, 22 Sep 2014 12:11:54 +0200 [thread overview]
Message-ID: <20140922101153.GN1470@ulmo> (raw)
In-Reply-To: <1411376456.2599.1.camel@pengutronix.de>
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On Mon, Sep 22, 2014 at 11:00:56AM +0200, Lucas Stach wrote:
> Am Freitag, den 19.09.2014, 15:53 -0400 schrieb Sean Paul:
> > Per NVidia, this clock rate should be around 70MHz in
> > order to properly sample reads on data lane 0. In order
> > to achieve this rate, we need to reparent the clock from
> > clk_m which can only achieve 12MHz. Add parent_lp to the
> > dts bindings and set the parent & rate on init.
> >
> > Signed-off-by: Sean Paul <seanpaul@chromium.org>
>
> NACK
>
> You are pushing SoC integration details into the binding of the device.
>
> You have two reasonable routes to go here: either the clock driver needs
> to be made smarter to reparent the clock in case the required clock rate
> could not be achieved with the current parent or you go the easy route
> and reparent the clock as part of the initial configuration.
Agreed. There doesn't seem to be a case where it would make sense to
have this configurable per-board. Can you achieve the same effect by
adding this to the clock initialization table?
Oh, I just see that we have this in the Tegra124 clock initialization
table:
{TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
{TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
Doesn't that work for you already? If not that'd be a bug that should be
fixed in the clock driver.
Thierry
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next prev parent reply other threads:[~2014-09-22 10:11 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-19 19:53 [PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate Sean Paul
2014-09-19 19:53 ` [PATCH 2/2] ARM: tegra: Add lp_parent clock to dsi Sean Paul
[not found] ` <1411156429-19797-1-git-send-email-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-09-22 7:28 ` [PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate Andrzej Hajda
2014-09-22 9:00 ` Lucas Stach
2014-09-22 10:11 ` Thierry Reding [this message]
2014-10-08 15:11 ` Peter De Schrijver
[not found] ` <20141008151155.GC4809-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2014-10-08 16:03 ` Sean Paul
2014-09-22 17:46 ` Mark Rutland
2014-09-23 7:22 ` Thierry Reding
2014-09-27 20:05 ` Mike Turquette
2014-09-29 8:17 ` Thierry Reding
2014-09-22 10:07 ` Thierry Reding
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