* [PATCH v2 0/2] mtd: nand: support ONFI timings mode retrieval for non-ONFI NANDs @ 2014-09-22 14:25 ` Boris BREZILLON 0 siblings, 0 replies; 10+ messages in thread From: Boris BREZILLON @ 2014-09-22 14:25 UTC (permalink / raw) To: David Woodhouse, Brian Norris, linux-mtd Cc: Boris BREZILLON, linux-sunxi, linux-kernel, Yassin Jaffer Hi, Following the series adding ONFI timing mode support, here is a series adding support for timing mode retrieval on non-ONFI NANDs. It just adds a new field to the nand_chip and nand_flash_dev struct so that anyone can define its chip requirements in the nand_ids table. The 2nd patch serves as an example and adds an entry for the Hynix H27UCG8T2ATR-BC NAND chip used on the Cubietruck board. Best Regards, Boris Changes since v1: - fix H27UCG8T2ATR-BC definition - rename onfi_timing_mode_ds field into onfi_timing_mode_default Boris BREZILLON (2): mtd: nand: support ONFI timing mode retrieval for non-ONFI NANDs mtd: nand: add Hynix's H27UCG8T2ATR-BC to nand_ids table drivers/mtd/nand/nand_base.c | 2 ++ drivers/mtd/nand/nand_ids.c | 4 ++++ include/linux/mtd/nand.h | 11 +++++++++++ 3 files changed, 17 insertions(+) -- 1.9.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 0/2] mtd: nand: support ONFI timings mode retrieval for non-ONFI NANDs @ 2014-09-22 14:25 ` Boris BREZILLON 0 siblings, 0 replies; 10+ messages in thread From: Boris BREZILLON @ 2014-09-22 14:25 UTC (permalink / raw) To: David Woodhouse, Brian Norris, linux-mtd Cc: linux-kernel, linux-sunxi, Yassin Jaffer, Boris BREZILLON Hi, Following the series adding ONFI timing mode support, here is a series adding support for timing mode retrieval on non-ONFI NANDs. It just adds a new field to the nand_chip and nand_flash_dev struct so that anyone can define its chip requirements in the nand_ids table. The 2nd patch serves as an example and adds an entry for the Hynix H27UCG8T2ATR-BC NAND chip used on the Cubietruck board. Best Regards, Boris Changes since v1: - fix H27UCG8T2ATR-BC definition - rename onfi_timing_mode_ds field into onfi_timing_mode_default Boris BREZILLON (2): mtd: nand: support ONFI timing mode retrieval for non-ONFI NANDs mtd: nand: add Hynix's H27UCG8T2ATR-BC to nand_ids table drivers/mtd/nand/nand_base.c | 2 ++ drivers/mtd/nand/nand_ids.c | 4 ++++ include/linux/mtd/nand.h | 11 +++++++++++ 3 files changed, 17 insertions(+) -- 1.9.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/2] mtd: nand: support ONFI timing mode retrieval for non-ONFI NANDs 2014-09-22 14:25 ` Boris BREZILLON @ 2014-09-22 14:25 ` Boris BREZILLON -1 siblings, 0 replies; 10+ messages in thread From: Boris BREZILLON @ 2014-09-22 14:25 UTC (permalink / raw) To: David Woodhouse, Brian Norris, linux-mtd Cc: Boris BREZILLON, linux-sunxi, linux-kernel, Yassin Jaffer Add an onfi_timing_mode_default field to nand_chip and nand_flash_dev in order to support NAND timings definition for non-ONFI NAND. NAND that support better timings mode than the default one have to define a new entry in the nand_ids table. The default timing mode should be deduced from timings description from the datasheet and the ONFI specification (www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf, chapter 4.15 "Timing Parameters"). You should choose the closest mode that fit the timings requirements of your NAND chip. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> --- drivers/mtd/nand/nand_base.c | 2 ++ include/linux/mtd/nand.h | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ae6e7c4..c37fa2a 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -3594,6 +3594,8 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, chip->options |= type->options; chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); chip->ecc_step_ds = NAND_ECC_STEP(type); + chip->onfi_timing_mode_default = + type->onfi_timing_mode_default; *busw = type->options & NAND_BUSWIDTH_16; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index b7c1199..e795fbf 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -587,6 +587,11 @@ struct nand_buffers { * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, * also from the datasheet. It is the recommended ECC step * size, if known; if unknown, set to zero. + * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is + * either deduced from the datasheet if the NAND + * chip is not ONFI compliant or set to 0 if it is + * (an ONFI chip is always configured in mode 0 + * after a NAND reset) * @numchips: [INTERN] number of physical chips * @chipsize: [INTERN] the size of one chip for multichip arrays * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 @@ -671,6 +676,7 @@ struct nand_chip { uint8_t bits_per_cell; uint16_t ecc_strength_ds; uint16_t ecc_step_ds; + int onfi_timing_mode_default; int badblockpos; int badblockbits; @@ -773,6 +779,10 @@ struct nand_chip { * @ecc_step_ds in nand_chip{}, also from the datasheet. * For example, the "4bit ECC for each 512Byte" can be set with * NAND_ECC_INFO(4, 512). + * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND + * reset. Should be deduced from timings described + * in the datasheet. + * */ struct nand_flash_dev { char *name; @@ -793,6 +803,7 @@ struct nand_flash_dev { uint16_t strength_ds; uint16_t step_ds; } ecc; + int onfi_timing_mode_default; }; /** -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 1/2] mtd: nand: support ONFI timing mode retrieval for non-ONFI NANDs @ 2014-09-22 14:25 ` Boris BREZILLON 0 siblings, 0 replies; 10+ messages in thread From: Boris BREZILLON @ 2014-09-22 14:25 UTC (permalink / raw) To: David Woodhouse, Brian Norris, linux-mtd Cc: linux-kernel, linux-sunxi, Yassin Jaffer, Boris BREZILLON Add an onfi_timing_mode_default field to nand_chip and nand_flash_dev in order to support NAND timings definition for non-ONFI NAND. NAND that support better timings mode than the default one have to define a new entry in the nand_ids table. The default timing mode should be deduced from timings description from the datasheet and the ONFI specification (www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf, chapter 4.15 "Timing Parameters"). You should choose the closest mode that fit the timings requirements of your NAND chip. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> --- drivers/mtd/nand/nand_base.c | 2 ++ include/linux/mtd/nand.h | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ae6e7c4..c37fa2a 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -3594,6 +3594,8 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, chip->options |= type->options; chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); chip->ecc_step_ds = NAND_ECC_STEP(type); + chip->onfi_timing_mode_default = + type->onfi_timing_mode_default; *busw = type->options & NAND_BUSWIDTH_16; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index b7c1199..e795fbf 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -587,6 +587,11 @@ struct nand_buffers { * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, * also from the datasheet. It is the recommended ECC step * size, if known; if unknown, set to zero. + * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is + * either deduced from the datasheet if the NAND + * chip is not ONFI compliant or set to 0 if it is + * (an ONFI chip is always configured in mode 0 + * after a NAND reset) * @numchips: [INTERN] number of physical chips * @chipsize: [INTERN] the size of one chip for multichip arrays * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 @@ -671,6 +676,7 @@ struct nand_chip { uint8_t bits_per_cell; uint16_t ecc_strength_ds; uint16_t ecc_step_ds; + int onfi_timing_mode_default; int badblockpos; int badblockbits; @@ -773,6 +779,10 @@ struct nand_chip { * @ecc_step_ds in nand_chip{}, also from the datasheet. * For example, the "4bit ECC for each 512Byte" can be set with * NAND_ECC_INFO(4, 512). + * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND + * reset. Should be deduced from timings described + * in the datasheet. + * */ struct nand_flash_dev { char *name; @@ -793,6 +803,7 @@ struct nand_flash_dev { uint16_t strength_ds; uint16_t step_ds; } ecc; + int onfi_timing_mode_default; }; /** -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] mtd: nand: support ONFI timing mode retrieval for non-ONFI NANDs 2014-09-22 14:25 ` Boris BREZILLON @ 2014-09-22 17:58 ` Brian Norris -1 siblings, 0 replies; 10+ messages in thread From: Brian Norris @ 2014-09-22 17:58 UTC (permalink / raw) To: Boris BREZILLON Cc: linux-mtd, linux-sunxi, David Woodhouse, linux-kernel, Yassin Jaffer On Mon, Sep 22, 2014 at 04:25:10PM +0200, Boris BREZILLON wrote: > Add an onfi_timing_mode_default field to nand_chip and nand_flash_dev in > order to support NAND timings definition for non-ONFI NAND. > > NAND that support better timings mode than the default one have to define > a new entry in the nand_ids table. > > The default timing mode should be deduced from timings description from > the datasheet and the ONFI specification > (www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf, chapter 4.15 > "Timing Parameters"). > You should choose the closest mode that fit the timings requirements of > your NAND chip. > > Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> You have some (new?) checkpatch warnings: WARNING: please, no space before tabs #49: FILE: include/linux/mtd/nand.h:591: + * ^I^I^I either deduced from the datasheet if the NAND$ WARNING: please, no space before tabs #50: FILE: include/linux/mtd/nand.h:592: + * ^I^I^I chip is not ONFI compliant or set to 0 if it is$ WARNING: please, no space before tabs #51: FILE: include/linux/mtd/nand.h:593: + * ^I^I^I (an ONFI chip is always configured in mode 0$ WARNING: please, no space before tabs #52: FILE: include/linux/mtd/nand.h:594: + * ^I^I^I after a NAND reset)$ total: 0 errors, 4 warnings, 43 lines checked Your patch has style problems, please review. If any of these errors are false positives, please report them to the maintainer, see CHECKPATCH in MAINTAINERS. Brian > --- > drivers/mtd/nand/nand_base.c | 2 ++ > include/linux/mtd/nand.h | 11 +++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c > index ae6e7c4..c37fa2a 100644 > --- a/drivers/mtd/nand/nand_base.c > +++ b/drivers/mtd/nand/nand_base.c > @@ -3594,6 +3594,8 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, > chip->options |= type->options; > chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); > chip->ecc_step_ds = NAND_ECC_STEP(type); > + chip->onfi_timing_mode_default = > + type->onfi_timing_mode_default; > > *busw = type->options & NAND_BUSWIDTH_16; > > diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h > index b7c1199..e795fbf 100644 > --- a/include/linux/mtd/nand.h > +++ b/include/linux/mtd/nand.h > @@ -587,6 +587,11 @@ struct nand_buffers { > * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, > * also from the datasheet. It is the recommended ECC step > * size, if known; if unknown, set to zero. > + * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is > + * either deduced from the datasheet if the NAND > + * chip is not ONFI compliant or set to 0 if it is > + * (an ONFI chip is always configured in mode 0 > + * after a NAND reset) > * @numchips: [INTERN] number of physical chips > * @chipsize: [INTERN] the size of one chip for multichip arrays > * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 > @@ -671,6 +676,7 @@ struct nand_chip { > uint8_t bits_per_cell; > uint16_t ecc_strength_ds; > uint16_t ecc_step_ds; > + int onfi_timing_mode_default; > int badblockpos; > int badblockbits; > > @@ -773,6 +779,10 @@ struct nand_chip { > * @ecc_step_ds in nand_chip{}, also from the datasheet. > * For example, the "4bit ECC for each 512Byte" can be set with > * NAND_ECC_INFO(4, 512). > + * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND > + * reset. Should be deduced from timings described > + * in the datasheet. > + * > */ > struct nand_flash_dev { > char *name; > @@ -793,6 +803,7 @@ struct nand_flash_dev { > uint16_t strength_ds; > uint16_t step_ds; > } ecc; > + int onfi_timing_mode_default; > }; > > /** > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] mtd: nand: support ONFI timing mode retrieval for non-ONFI NANDs @ 2014-09-22 17:58 ` Brian Norris 0 siblings, 0 replies; 10+ messages in thread From: Brian Norris @ 2014-09-22 17:58 UTC (permalink / raw) To: Boris BREZILLON Cc: David Woodhouse, linux-mtd, linux-kernel, linux-sunxi, Yassin Jaffer On Mon, Sep 22, 2014 at 04:25:10PM +0200, Boris BREZILLON wrote: > Add an onfi_timing_mode_default field to nand_chip and nand_flash_dev in > order to support NAND timings definition for non-ONFI NAND. > > NAND that support better timings mode than the default one have to define > a new entry in the nand_ids table. > > The default timing mode should be deduced from timings description from > the datasheet and the ONFI specification > (www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf, chapter 4.15 > "Timing Parameters"). > You should choose the closest mode that fit the timings requirements of > your NAND chip. > > Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> You have some (new?) checkpatch warnings: WARNING: please, no space before tabs #49: FILE: include/linux/mtd/nand.h:591: + * ^I^I^I either deduced from the datasheet if the NAND$ WARNING: please, no space before tabs #50: FILE: include/linux/mtd/nand.h:592: + * ^I^I^I chip is not ONFI compliant or set to 0 if it is$ WARNING: please, no space before tabs #51: FILE: include/linux/mtd/nand.h:593: + * ^I^I^I (an ONFI chip is always configured in mode 0$ WARNING: please, no space before tabs #52: FILE: include/linux/mtd/nand.h:594: + * ^I^I^I after a NAND reset)$ total: 0 errors, 4 warnings, 43 lines checked Your patch has style problems, please review. If any of these errors are false positives, please report them to the maintainer, see CHECKPATCH in MAINTAINERS. Brian > --- > drivers/mtd/nand/nand_base.c | 2 ++ > include/linux/mtd/nand.h | 11 +++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c > index ae6e7c4..c37fa2a 100644 > --- a/drivers/mtd/nand/nand_base.c > +++ b/drivers/mtd/nand/nand_base.c > @@ -3594,6 +3594,8 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, > chip->options |= type->options; > chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); > chip->ecc_step_ds = NAND_ECC_STEP(type); > + chip->onfi_timing_mode_default = > + type->onfi_timing_mode_default; > > *busw = type->options & NAND_BUSWIDTH_16; > > diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h > index b7c1199..e795fbf 100644 > --- a/include/linux/mtd/nand.h > +++ b/include/linux/mtd/nand.h > @@ -587,6 +587,11 @@ struct nand_buffers { > * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, > * also from the datasheet. It is the recommended ECC step > * size, if known; if unknown, set to zero. > + * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is > + * either deduced from the datasheet if the NAND > + * chip is not ONFI compliant or set to 0 if it is > + * (an ONFI chip is always configured in mode 0 > + * after a NAND reset) > * @numchips: [INTERN] number of physical chips > * @chipsize: [INTERN] the size of one chip for multichip arrays > * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 > @@ -671,6 +676,7 @@ struct nand_chip { > uint8_t bits_per_cell; > uint16_t ecc_strength_ds; > uint16_t ecc_step_ds; > + int onfi_timing_mode_default; > int badblockpos; > int badblockbits; > > @@ -773,6 +779,10 @@ struct nand_chip { > * @ecc_step_ds in nand_chip{}, also from the datasheet. > * For example, the "4bit ECC for each 512Byte" can be set with > * NAND_ECC_INFO(4, 512). > + * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND > + * reset. Should be deduced from timings described > + * in the datasheet. > + * > */ > struct nand_flash_dev { > char *name; > @@ -793,6 +803,7 @@ struct nand_flash_dev { > uint16_t strength_ds; > uint16_t step_ds; > } ecc; > + int onfi_timing_mode_default; > }; > > /** > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] mtd: nand: support ONFI timing mode retrieval for non-ONFI NANDs 2014-09-22 17:58 ` Brian Norris @ 2014-09-22 18:13 ` Boris BREZILLON -1 siblings, 0 replies; 10+ messages in thread From: Boris BREZILLON @ 2014-09-22 18:13 UTC (permalink / raw) To: Brian Norris Cc: linux-mtd, linux-sunxi, David Woodhouse, linux-kernel, Yassin Jaffer On Mon, 22 Sep 2014 10:58:34 -0700 Brian Norris <computersforpeace@gmail.com> wrote: > On Mon, Sep 22, 2014 at 04:25:10PM +0200, Boris BREZILLON wrote: > > Add an onfi_timing_mode_default field to nand_chip and nand_flash_dev in > > order to support NAND timings definition for non-ONFI NAND. > > > > NAND that support better timings mode than the default one have to define > > a new entry in the nand_ids table. > > > > The default timing mode should be deduced from timings description from > > the datasheet and the ONFI specification > > (www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf, chapter 4.15 > > "Timing Parameters"). > > You should choose the closest mode that fit the timings requirements of > > your NAND chip. > > > > Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> > > You have some (new?) checkpatch warnings: > Sorry for that. I just sent a new version fixing those warnings. Best Regards, Boris -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] mtd: nand: support ONFI timing mode retrieval for non-ONFI NANDs @ 2014-09-22 18:13 ` Boris BREZILLON 0 siblings, 0 replies; 10+ messages in thread From: Boris BREZILLON @ 2014-09-22 18:13 UTC (permalink / raw) To: Brian Norris Cc: David Woodhouse, linux-mtd, linux-kernel, linux-sunxi, Yassin Jaffer On Mon, 22 Sep 2014 10:58:34 -0700 Brian Norris <computersforpeace@gmail.com> wrote: > On Mon, Sep 22, 2014 at 04:25:10PM +0200, Boris BREZILLON wrote: > > Add an onfi_timing_mode_default field to nand_chip and nand_flash_dev in > > order to support NAND timings definition for non-ONFI NAND. > > > > NAND that support better timings mode than the default one have to define > > a new entry in the nand_ids table. > > > > The default timing mode should be deduced from timings description from > > the datasheet and the ONFI specification > > (www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf, chapter 4.15 > > "Timing Parameters"). > > You should choose the closest mode that fit the timings requirements of > > your NAND chip. > > > > Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> > > You have some (new?) checkpatch warnings: > Sorry for that. I just sent a new version fixing those warnings. Best Regards, Boris -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/2] mtd: nand: add Hynix's H27UCG8T2ATR-BC to nand_ids table 2014-09-22 14:25 ` Boris BREZILLON @ 2014-09-22 14:25 ` Boris BREZILLON -1 siblings, 0 replies; 10+ messages in thread From: Boris BREZILLON @ 2014-09-22 14:25 UTC (permalink / raw) To: David Woodhouse, Brian Norris, linux-mtd Cc: Boris BREZILLON, linux-sunxi, linux-kernel, Yassin Jaffer Add the full description of the Hynix H27UCG8T2ATR-BC NAND chip in the nand_ids table so that we can later use the NAND ECC infos and ONFI timings mode in controller drivers. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> --- drivers/mtd/nand/nand_ids.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 3d7c89f..fbde8910 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -46,6 +46,10 @@ struct nand_flash_dev nand_flash_ids[] = { {"SDTNRGAMA 64G 3.3V 8-bit", { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} }, SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, + {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", + { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, + SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K), + 4 }, LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/2] mtd: nand: add Hynix's H27UCG8T2ATR-BC to nand_ids table @ 2014-09-22 14:25 ` Boris BREZILLON 0 siblings, 0 replies; 10+ messages in thread From: Boris BREZILLON @ 2014-09-22 14:25 UTC (permalink / raw) To: David Woodhouse, Brian Norris, linux-mtd Cc: linux-kernel, linux-sunxi, Yassin Jaffer, Boris BREZILLON Add the full description of the Hynix H27UCG8T2ATR-BC NAND chip in the nand_ids table so that we can later use the NAND ECC infos and ONFI timings mode in controller drivers. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> --- drivers/mtd/nand/nand_ids.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 3d7c89f..fbde8910 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -46,6 +46,10 @@ struct nand_flash_dev nand_flash_ids[] = { {"SDTNRGAMA 64G 3.3V 8-bit", { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} }, SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, + {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", + { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, + SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K), + 4 }, LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2014-09-22 18:13 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-09-22 14:25 [PATCH v2 0/2] mtd: nand: support ONFI timings mode retrieval for non-ONFI NANDs Boris BREZILLON 2014-09-22 14:25 ` Boris BREZILLON 2014-09-22 14:25 ` [PATCH v2 1/2] mtd: nand: support ONFI timing " Boris BREZILLON 2014-09-22 14:25 ` Boris BREZILLON 2014-09-22 17:58 ` Brian Norris 2014-09-22 17:58 ` Brian Norris 2014-09-22 18:13 ` Boris BREZILLON 2014-09-22 18:13 ` Boris BREZILLON 2014-09-22 14:25 ` [PATCH v2 2/2] mtd: nand: add Hynix's H27UCG8T2ATR-BC to nand_ids table Boris BREZILLON 2014-09-22 14:25 ` Boris BREZILLON
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