* [PATCH v3 0/3] Add clock binding id for rk3288 @ 2014-09-25 7:48 ` Kever Yang 0 siblings, 0 replies; 15+ messages in thread From: Kever Yang @ 2014-09-25 7:48 UTC (permalink / raw) To: linux-arm-kernel This patch add some clock binding id for different modules that under development and going to send upstream. This patch also add the clock node in PD_VIDEO. Changes in v3: - add a fix factor - introduce a virtual node to implement the clock struct Changes in v2: - split into two patches of add clock node in PD_VIDEO and use new defined clock ID - split out the patch Kever Yang (3): clk: rockchip: add some needed clock binding id for rk3288 clk: rockchip: use the clock id for nodes init clk: rockchip: add clock node in PD_VIDEO drivers/clk/rockchip/clk-rk3288.c | 88 +++++++++++++++++++++------------- include/dt-bindings/clock/rk3288-cru.h | 38 ++++++++++++++- 2 files changed, 91 insertions(+), 35 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 0/3] Add clock binding id for rk3288 @ 2014-09-25 7:48 ` Kever Yang 0 siblings, 0 replies; 15+ messages in thread From: Kever Yang @ 2014-09-25 7:48 UTC (permalink / raw) To: heiko, Mike Turquette Cc: dianders, sonnyrao, addy.ke, cf, xjq, hj, huangtao, linux-rockchip, Kever Yang, devicetree, Kumar Gala, linux-kernel, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland, linux-arm-kernel This patch add some clock binding id for different modules that under development and going to send upstream. This patch also add the clock node in PD_VIDEO. Changes in v3: - add a fix factor - introduce a virtual node to implement the clock struct Changes in v2: - split into two patches of add clock node in PD_VIDEO and use new defined clock ID - split out the patch Kever Yang (3): clk: rockchip: add some needed clock binding id for rk3288 clk: rockchip: use the clock id for nodes init clk: rockchip: add clock node in PD_VIDEO drivers/clk/rockchip/clk-rk3288.c | 88 +++++++++++++++++++++------------- include/dt-bindings/clock/rk3288-cru.h | 38 ++++++++++++++- 2 files changed, 91 insertions(+), 35 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 1/3] clk: rockchip: add some needed clock binding id for rk3288 2014-09-25 7:48 ` Kever Yang (?) @ 2014-09-25 7:48 ` Kever Yang [not found] ` <1411631328-14973-2-git-send-email-kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org> -1 siblings, 1 reply; 15+ messages in thread From: Kever Yang @ 2014-09-25 7:48 UTC (permalink / raw) To: heiko, Mike Turquette Cc: dianders, sonnyrao, addy.ke, cf, xjq, hj, huangtao, linux-rockchip, Kever Yang, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, devicetree, linux-kernel This patch add some clock binding id for different modules that under development and going to send upstream. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> --- Changes in v3: None Changes in v2: None include/dt-bindings/clock/rk3288-cru.h | 38 +++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index ebcb460..ee579ff 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -61,6 +61,15 @@ #define SCLK_LCDC_PWM1 101 #define SCLK_MAC_RX 102 #define SCLK_MAC_TX 103 +#define SCLK_EDP_24M 104 +#define SCLK_EDP 105 +#define SCLK_RGA 106 +#define SCLK_ISP 107 +#define SCLK_ISP_JPE 108 +#define SCLK_HDMI_HDCP 109 +#define SCLK_HDMI_CEC 110 +#define SCLK_HEVC_CABAC 111 +#define SCLK_HEVC_CORE 112 #define DCLK_VOP0 190 #define DCLK_VOP1 191 @@ -75,6 +84,16 @@ #define ACLK_VOP1 198 #define ACLK_CRYPTO 199 #define ACLK_RGA 200 +#define ACLK_RGA_NIU 201 +#define ACLK_IEP 202 +#define ACLK_VIO0_NIU 203 +#define ACLK_VIP 204 +#define ACLK_ISP 205 +#define ACLK_VIO1_NIU 206 +#define ACLK_HEVC 207 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 /* pclk gates */ #define PCLK_GPIO0 320 @@ -112,6 +131,15 @@ #define PCLK_PS2C 352 #define PCLK_TIMER 353 #define PCLK_TZPC 354 +#define PCLK_EDP_CTRL 355 +#define PCLK_MIPI_DSI0 356 +#define PCLK_MIPI_DSI1 357 +#define PCLK_MIPI_CSI 358 +#define PCLK_LVDS_PHY 359 +#define PCLK_HDMI_CTRL 360 +#define PCLK_VIO2_H2P 361 +#define PCLK_CPU 362 +#define PCLK_PERI 363 /* hclk gates */ #define HCLK_GPS 448 @@ -137,8 +165,16 @@ #define HCLK_IEP 468 #define HCLK_ISP 469 #define HCLK_RGA 470 +#define HCLK_VIO_AHB_ARBI 471 +#define HCLK_VIO_NIU 472 +#define HCLK_VIP 473 +#define HCLK_VIO2_H2P 474 +#define HCLK_HEVC 475 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 -#define CLK_NR_CLKS (HCLK_RGA + 1) +#define CLK_NR_CLKS (HCLK_PERI + 1) /* soft-reset indices */ #define SRST_CORE0 0 -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
[parent not found: <1411631328-14973-2-git-send-email-kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [PATCH v3 1/3] clk: rockchip: add some needed clock binding id for rk3288 2014-09-25 7:48 ` [PATCH v3 1/3] clk: rockchip: add some needed " Kever Yang @ 2014-09-25 22:07 ` Mike Turquette 0 siblings, 0 replies; 15+ messages in thread From: Mike Turquette @ 2014-09-25 22:07 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: dianders-F7+t8E8rja9g9hUCZPvPmw, sonnyrao-F7+t8E8rja9g9hUCZPvPmw, addy.ke-TNX95d0MmH7DzftRWevZcw, cf-TNX95d0MmH7DzftRWevZcw, xjq-TNX95d0MmH7DzftRWevZcw, hj-TNX95d0MmH7DzftRWevZcw, huangtao-TNX95d0MmH7DzftRWevZcw, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kever Yang, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA Quoting Kever Yang (2014-09-25 00:48:45) > This patch add some clock binding id for different modules > that under development and going to send upstream. > > Signed-off-by: Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > Reviewed-by: Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> > Reviewed-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> Applied the V1 of this patch from another thread, but seems to be no delta. Regards, Mike > --- > > Changes in v3: None > Changes in v2: None > > include/dt-bindings/clock/rk3288-cru.h | 38 +++++++++++++++++++++++++++++++++- > 1 file changed, 37 insertions(+), 1 deletion(-) > > diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h > index ebcb460..ee579ff 100644 > --- a/include/dt-bindings/clock/rk3288-cru.h > +++ b/include/dt-bindings/clock/rk3288-cru.h > @@ -61,6 +61,15 @@ > #define SCLK_LCDC_PWM1 101 > #define SCLK_MAC_RX 102 > #define SCLK_MAC_TX 103 > +#define SCLK_EDP_24M 104 > +#define SCLK_EDP 105 > +#define SCLK_RGA 106 > +#define SCLK_ISP 107 > +#define SCLK_ISP_JPE 108 > +#define SCLK_HDMI_HDCP 109 > +#define SCLK_HDMI_CEC 110 > +#define SCLK_HEVC_CABAC 111 > +#define SCLK_HEVC_CORE 112 > > #define DCLK_VOP0 190 > #define DCLK_VOP1 191 > @@ -75,6 +84,16 @@ > #define ACLK_VOP1 198 > #define ACLK_CRYPTO 199 > #define ACLK_RGA 200 > +#define ACLK_RGA_NIU 201 > +#define ACLK_IEP 202 > +#define ACLK_VIO0_NIU 203 > +#define ACLK_VIP 204 > +#define ACLK_ISP 205 > +#define ACLK_VIO1_NIU 206 > +#define ACLK_HEVC 207 > +#define ACLK_VCODEC 208 > +#define ACLK_CPU 209 > +#define ACLK_PERI 210 > > /* pclk gates */ > #define PCLK_GPIO0 320 > @@ -112,6 +131,15 @@ > #define PCLK_PS2C 352 > #define PCLK_TIMER 353 > #define PCLK_TZPC 354 > +#define PCLK_EDP_CTRL 355 > +#define PCLK_MIPI_DSI0 356 > +#define PCLK_MIPI_DSI1 357 > +#define PCLK_MIPI_CSI 358 > +#define PCLK_LVDS_PHY 359 > +#define PCLK_HDMI_CTRL 360 > +#define PCLK_VIO2_H2P 361 > +#define PCLK_CPU 362 > +#define PCLK_PERI 363 > > /* hclk gates */ > #define HCLK_GPS 448 > @@ -137,8 +165,16 @@ > #define HCLK_IEP 468 > #define HCLK_ISP 469 > #define HCLK_RGA 470 > +#define HCLK_VIO_AHB_ARBI 471 > +#define HCLK_VIO_NIU 472 > +#define HCLK_VIP 473 > +#define HCLK_VIO2_H2P 474 > +#define HCLK_HEVC 475 > +#define HCLK_VCODEC 476 > +#define HCLK_CPU 477 > +#define HCLK_PERI 478 > > -#define CLK_NR_CLKS (HCLK_RGA + 1) > +#define CLK_NR_CLKS (HCLK_PERI + 1) > > /* soft-reset indices */ > #define SRST_CORE0 0 > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/3] clk: rockchip: add some needed clock binding id for rk3288 @ 2014-09-25 22:07 ` Mike Turquette 0 siblings, 0 replies; 15+ messages in thread From: Mike Turquette @ 2014-09-25 22:07 UTC (permalink / raw) To: Kever Yang, heiko Cc: dianders, sonnyrao, addy.ke, cf, xjq, hj, huangtao, linux-rockchip, Kever Yang, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, devicetree, linux-kernel Quoting Kever Yang (2014-09-25 00:48:45) > This patch add some clock binding id for different modules > that under development and going to send upstream. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Reviewed-by: Doug Anderson <dianders@chromium.org> > Reviewed-by: Heiko Stuebner <heiko@sntech.de> Applied the V1 of this patch from another thread, but seems to be no delta. Regards, Mike > --- > > Changes in v3: None > Changes in v2: None > > include/dt-bindings/clock/rk3288-cru.h | 38 +++++++++++++++++++++++++++++++++- > 1 file changed, 37 insertions(+), 1 deletion(-) > > diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h > index ebcb460..ee579ff 100644 > --- a/include/dt-bindings/clock/rk3288-cru.h > +++ b/include/dt-bindings/clock/rk3288-cru.h > @@ -61,6 +61,15 @@ > #define SCLK_LCDC_PWM1 101 > #define SCLK_MAC_RX 102 > #define SCLK_MAC_TX 103 > +#define SCLK_EDP_24M 104 > +#define SCLK_EDP 105 > +#define SCLK_RGA 106 > +#define SCLK_ISP 107 > +#define SCLK_ISP_JPE 108 > +#define SCLK_HDMI_HDCP 109 > +#define SCLK_HDMI_CEC 110 > +#define SCLK_HEVC_CABAC 111 > +#define SCLK_HEVC_CORE 112 > > #define DCLK_VOP0 190 > #define DCLK_VOP1 191 > @@ -75,6 +84,16 @@ > #define ACLK_VOP1 198 > #define ACLK_CRYPTO 199 > #define ACLK_RGA 200 > +#define ACLK_RGA_NIU 201 > +#define ACLK_IEP 202 > +#define ACLK_VIO0_NIU 203 > +#define ACLK_VIP 204 > +#define ACLK_ISP 205 > +#define ACLK_VIO1_NIU 206 > +#define ACLK_HEVC 207 > +#define ACLK_VCODEC 208 > +#define ACLK_CPU 209 > +#define ACLK_PERI 210 > > /* pclk gates */ > #define PCLK_GPIO0 320 > @@ -112,6 +131,15 @@ > #define PCLK_PS2C 352 > #define PCLK_TIMER 353 > #define PCLK_TZPC 354 > +#define PCLK_EDP_CTRL 355 > +#define PCLK_MIPI_DSI0 356 > +#define PCLK_MIPI_DSI1 357 > +#define PCLK_MIPI_CSI 358 > +#define PCLK_LVDS_PHY 359 > +#define PCLK_HDMI_CTRL 360 > +#define PCLK_VIO2_H2P 361 > +#define PCLK_CPU 362 > +#define PCLK_PERI 363 > > /* hclk gates */ > #define HCLK_GPS 448 > @@ -137,8 +165,16 @@ > #define HCLK_IEP 468 > #define HCLK_ISP 469 > #define HCLK_RGA 470 > +#define HCLK_VIO_AHB_ARBI 471 > +#define HCLK_VIO_NIU 472 > +#define HCLK_VIP 473 > +#define HCLK_VIO2_H2P 474 > +#define HCLK_HEVC 475 > +#define HCLK_VCODEC 476 > +#define HCLK_CPU 477 > +#define HCLK_PERI 478 > > -#define CLK_NR_CLKS (HCLK_RGA + 1) > +#define CLK_NR_CLKS (HCLK_PERI + 1) > > /* soft-reset indices */ > #define SRST_CORE0 0 > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 2/3] clk: rockchip: use the clock id for nodes init 2014-09-25 7:48 ` Kever Yang @ 2014-09-25 7:48 ` Kever Yang -1 siblings, 0 replies; 15+ messages in thread From: Kever Yang @ 2014-09-25 7:48 UTC (permalink / raw) To: linux-arm-kernel This patch use the new defined clock ID to initial the clock nodes. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> --- Changes in v3: None Changes in v2: - split into two patches of add clock node in PD_VIDEO and use new defined clock ID drivers/clk/rockchip/clk-rk3288.c | 68 +++++++++++++++++++-------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index a58b0b3..dd204cb 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -219,12 +219,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS), DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0, RK3288_CLKSEL_CON(1), 0, 3, DFLAGS), - GATE(0, "aclk_cpu", "aclk_cpu_pre", 0, + GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, RK3288_CLKGATE_CON(0), 3, GFLAGS), - COMPOSITE_NOMUX(0, "pclk_cpu", "aclk_cpu_pre", 0, + COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0, RK3288_CLKSEL_CON(1), 12, 3, DFLAGS, RK3288_CLKGATE_CON(0), 5, GFLAGS), - COMPOSITE_NOMUX_DIVTBL(0, "hclk_cpu", "aclk_cpu_pre", 0, + COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0, RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t, RK3288_CLKGATE_CON(0), 4, GFLAGS), GATE(0, "c2c_host", "aclk_cpu_src", 0, @@ -309,7 +309,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3288_CLKGATE_CON(3), 5, GFLAGS), - COMPOSITE(0, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0, + COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 4, GFLAGS), @@ -320,35 +320,35 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS, RK3288_CLKGATE_CON(3), 3, GFLAGS), - COMPOSITE_NODIV(0, "sclk_edp_24m", mux_edp_24m_p, 0, + COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0, RK3288_CLKSEL_CON(28), 15, 1, MFLAGS, RK3288_CLKGATE_CON(3), 12, GFLAGS), - COMPOSITE(0, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS, RK3288_CLKGATE_CON(3), 13, GFLAGS), - COMPOSITE(0, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS, RK3288_CLKGATE_CON(3), 14, GFLAGS), - COMPOSITE(0, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS, RK3288_CLKGATE_CON(3), 15, GFLAGS), - GATE(0, "sclk_hdmi_hdcp", "xin24m", 0, + GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, RK3288_CLKGATE_CON(5), 12, GFLAGS), - GATE(0, "sclk_hdmi_cec", "xin32k", 0, + GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0, RK3288_CLKGATE_CON(5), 11, GFLAGS), - COMPOSITE(0, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(13), 13, GFLAGS), - DIV(0, "hclk_hevc", "aclk_hevc", 0, + DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0, RK3288_CLKSEL_CON(40), 12, 2, DFLAGS), - COMPOSITE(0, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3288_CLKGATE_CON(13), 14, GFLAGS), - COMPOSITE(0, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(13), 15, GFLAGS), @@ -371,13 +371,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, RK3288_CLKGATE_CON(2), 0, GFLAGS), - COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_src", 0, + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK3288_CLKGATE_CON(2), 3, GFLAGS), - COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_src", 0, + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK3288_CLKGATE_CON(2), 2, GFLAGS), - GATE(0, "aclk_peri", "aclk_peri_src", 0, + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, RK3288_CLKGATE_CON(2), 1, GFLAGS), /* @@ -643,34 +643,34 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS), GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS), GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS), - GATE(0, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS), - GATE(0, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS), - GATE(0, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS), + GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS), + GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS), + GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS), GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS), GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS), - GATE(0, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS), - GATE(0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS), - GATE(0, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS), - GATE(0, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS), - GATE(0, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS), - GATE(0, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS), - GATE(0, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS), - GATE(0, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS), + GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS), + GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS), + GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS), + GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS), + GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS), + GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS), + GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS), + GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS), /* aclk_vio0 gates */ GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS), - GATE(0, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS), - GATE(0, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS), - GATE(0, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS), + GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS), + GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS), + GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS), /* aclk_vio1 gates */ GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS), - GATE(0, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS), - GATE(0, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS), + GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS), + GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS), /* aclk_rga_pre gates */ GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS), - GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS), + GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS), /* * Other ungrouped clocks. -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 2/3] clk: rockchip: use the clock id for nodes init @ 2014-09-25 7:48 ` Kever Yang 0 siblings, 0 replies; 15+ messages in thread From: Kever Yang @ 2014-09-25 7:48 UTC (permalink / raw) To: heiko, Mike Turquette Cc: dianders, sonnyrao, addy.ke, cf, xjq, hj, huangtao, linux-rockchip, Kever Yang, linux-arm-kernel, linux-kernel This patch use the new defined clock ID to initial the clock nodes. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> --- Changes in v3: None Changes in v2: - split into two patches of add clock node in PD_VIDEO and use new defined clock ID drivers/clk/rockchip/clk-rk3288.c | 68 +++++++++++++++++++-------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index a58b0b3..dd204cb 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -219,12 +219,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS), DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0, RK3288_CLKSEL_CON(1), 0, 3, DFLAGS), - GATE(0, "aclk_cpu", "aclk_cpu_pre", 0, + GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, RK3288_CLKGATE_CON(0), 3, GFLAGS), - COMPOSITE_NOMUX(0, "pclk_cpu", "aclk_cpu_pre", 0, + COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0, RK3288_CLKSEL_CON(1), 12, 3, DFLAGS, RK3288_CLKGATE_CON(0), 5, GFLAGS), - COMPOSITE_NOMUX_DIVTBL(0, "hclk_cpu", "aclk_cpu_pre", 0, + COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0, RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t, RK3288_CLKGATE_CON(0), 4, GFLAGS), GATE(0, "c2c_host", "aclk_cpu_src", 0, @@ -309,7 +309,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3288_CLKGATE_CON(3), 5, GFLAGS), - COMPOSITE(0, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0, + COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 4, GFLAGS), @@ -320,35 +320,35 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS, RK3288_CLKGATE_CON(3), 3, GFLAGS), - COMPOSITE_NODIV(0, "sclk_edp_24m", mux_edp_24m_p, 0, + COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0, RK3288_CLKSEL_CON(28), 15, 1, MFLAGS, RK3288_CLKGATE_CON(3), 12, GFLAGS), - COMPOSITE(0, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS, RK3288_CLKGATE_CON(3), 13, GFLAGS), - COMPOSITE(0, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS, RK3288_CLKGATE_CON(3), 14, GFLAGS), - COMPOSITE(0, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS, RK3288_CLKGATE_CON(3), 15, GFLAGS), - GATE(0, "sclk_hdmi_hdcp", "xin24m", 0, + GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, RK3288_CLKGATE_CON(5), 12, GFLAGS), - GATE(0, "sclk_hdmi_cec", "xin32k", 0, + GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0, RK3288_CLKGATE_CON(5), 11, GFLAGS), - COMPOSITE(0, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(13), 13, GFLAGS), - DIV(0, "hclk_hevc", "aclk_hevc", 0, + DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0, RK3288_CLKSEL_CON(40), 12, 2, DFLAGS), - COMPOSITE(0, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3288_CLKGATE_CON(13), 14, GFLAGS), - COMPOSITE(0, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0, + COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(13), 15, GFLAGS), @@ -371,13 +371,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, RK3288_CLKGATE_CON(2), 0, GFLAGS), - COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_src", 0, + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK3288_CLKGATE_CON(2), 3, GFLAGS), - COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_src", 0, + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK3288_CLKGATE_CON(2), 2, GFLAGS), - GATE(0, "aclk_peri", "aclk_peri_src", 0, + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, RK3288_CLKGATE_CON(2), 1, GFLAGS), /* @@ -643,34 +643,34 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS), GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS), GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS), - GATE(0, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS), - GATE(0, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS), - GATE(0, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS), + GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS), + GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS), + GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS), GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS), GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS), - GATE(0, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS), - GATE(0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS), - GATE(0, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS), - GATE(0, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS), - GATE(0, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS), - GATE(0, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS), - GATE(0, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS), - GATE(0, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS), + GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS), + GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS), + GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS), + GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS), + GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS), + GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS), + GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS), + GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS), /* aclk_vio0 gates */ GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS), - GATE(0, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS), - GATE(0, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS), - GATE(0, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS), + GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS), + GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS), + GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS), /* aclk_vio1 gates */ GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS), - GATE(0, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS), - GATE(0, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS), + GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS), + GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS), /* aclk_rga_pre gates */ GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS), - GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS), + GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS), /* * Other ungrouped clocks. -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 2/3] clk: rockchip: use the clock id for nodes init 2014-09-25 7:48 ` Kever Yang @ 2014-09-25 22:06 ` Mike Turquette -1 siblings, 0 replies; 15+ messages in thread From: Mike Turquette @ 2014-09-25 22:06 UTC (permalink / raw) To: linux-arm-kernel Quoting Kever Yang (2014-09-25 00:48:46) > This patch use the new defined clock ID to initial the clock nodes. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Reviewed-by: Doug Anderson <dianders@chromium.org> > Reviewed-by: Heiko Stuebner <heiko@sntech.de> Oops, I applied the old one too quickly. I've replaced the V1 patch in the clk tree with this version. Thanks Doug for pointing that out. Regards, Mike > --- > > Changes in v3: None > Changes in v2: > - split into two patches of add clock node in PD_VIDEO and > use new defined clock ID > > drivers/clk/rockchip/clk-rk3288.c | 68 +++++++++++++++++++-------------------- > 1 file changed, 34 insertions(+), 34 deletions(-) > > diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c > index a58b0b3..dd204cb 100644 > --- a/drivers/clk/rockchip/clk-rk3288.c > +++ b/drivers/clk/rockchip/clk-rk3288.c > @@ -219,12 +219,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS), > DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0, > RK3288_CLKSEL_CON(1), 0, 3, DFLAGS), > - GATE(0, "aclk_cpu", "aclk_cpu_pre", 0, > + GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, > RK3288_CLKGATE_CON(0), 3, GFLAGS), > - COMPOSITE_NOMUX(0, "pclk_cpu", "aclk_cpu_pre", 0, > + COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0, > RK3288_CLKSEL_CON(1), 12, 3, DFLAGS, > RK3288_CLKGATE_CON(0), 5, GFLAGS), > - COMPOSITE_NOMUX_DIVTBL(0, "hclk_cpu", "aclk_cpu_pre", 0, > + COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0, > RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t, > RK3288_CLKGATE_CON(0), 4, GFLAGS), > GATE(0, "c2c_host", "aclk_cpu_src", 0, > @@ -309,7 +309,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0, > RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS, > RK3288_CLKGATE_CON(3), 5, GFLAGS), > - COMPOSITE(0, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0, > + COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0, > RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, > RK3288_CLKGATE_CON(3), 4, GFLAGS), > > @@ -320,35 +320,35 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS, > RK3288_CLKGATE_CON(3), 3, GFLAGS), > > - COMPOSITE_NODIV(0, "sclk_edp_24m", mux_edp_24m_p, 0, > + COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0, > RK3288_CLKSEL_CON(28), 15, 1, MFLAGS, > RK3288_CLKGATE_CON(3), 12, GFLAGS), > - COMPOSITE(0, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0, > + COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0, > RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS, > RK3288_CLKGATE_CON(3), 13, GFLAGS), > > - COMPOSITE(0, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0, > + COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0, > RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS, > RK3288_CLKGATE_CON(3), 14, GFLAGS), > - COMPOSITE(0, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0, > + COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0, > RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS, > RK3288_CLKGATE_CON(3), 15, GFLAGS), > > - GATE(0, "sclk_hdmi_hdcp", "xin24m", 0, > + GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, > RK3288_CLKGATE_CON(5), 12, GFLAGS), > - GATE(0, "sclk_hdmi_cec", "xin32k", 0, > + GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0, > RK3288_CLKGATE_CON(5), 11, GFLAGS), > > - COMPOSITE(0, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0, > + COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0, > RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS, > RK3288_CLKGATE_CON(13), 13, GFLAGS), > - DIV(0, "hclk_hevc", "aclk_hevc", 0, > + DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0, > RK3288_CLKSEL_CON(40), 12, 2, DFLAGS), > > - COMPOSITE(0, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0, > + COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0, > RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, > RK3288_CLKGATE_CON(13), 14, GFLAGS), > - COMPOSITE(0, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0, > + COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0, > RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, > RK3288_CLKGATE_CON(13), 15, GFLAGS), > > @@ -371,13 +371,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0, > RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, > RK3288_CLKGATE_CON(2), 0, GFLAGS), > - COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_src", 0, > + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, > RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, > RK3288_CLKGATE_CON(2), 3, GFLAGS), > - COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_src", 0, > + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, > RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, > RK3288_CLKGATE_CON(2), 2, GFLAGS), > - GATE(0, "aclk_peri", "aclk_peri_src", 0, > + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, > RK3288_CLKGATE_CON(2), 1, GFLAGS), > > /* > @@ -643,34 +643,34 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS), > GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS), > GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS), > - GATE(0, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS), > - GATE(0, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS), > - GATE(0, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS), > + GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS), > + GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS), > + GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS), > GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS), > GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS), > - GATE(0, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS), > - GATE(0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS), > - GATE(0, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS), > - GATE(0, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS), > - GATE(0, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS), > - GATE(0, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS), > - GATE(0, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS), > - GATE(0, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS), > + GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS), > + GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS), > + GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS), > + GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS), > + GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS), > + GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS), > + GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS), > + GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS), > > /* aclk_vio0 gates */ > GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS), > - GATE(0, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS), > - GATE(0, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS), > - GATE(0, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS), > + GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS), > + GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS), > + GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS), > > /* aclk_vio1 gates */ > GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS), > - GATE(0, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS), > - GATE(0, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS), > + GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS), > + GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS), > > /* aclk_rga_pre gates */ > GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS), > - GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS), > + GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS), > > /* > * Other ungrouped clocks. > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/3] clk: rockchip: use the clock id for nodes init @ 2014-09-25 22:06 ` Mike Turquette 0 siblings, 0 replies; 15+ messages in thread From: Mike Turquette @ 2014-09-25 22:06 UTC (permalink / raw) To: Kever Yang, heiko Cc: dianders, sonnyrao, addy.ke, cf, xjq, hj, huangtao, linux-rockchip, Kever Yang, linux-arm-kernel, linux-kernel Quoting Kever Yang (2014-09-25 00:48:46) > This patch use the new defined clock ID to initial the clock nodes. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Reviewed-by: Doug Anderson <dianders@chromium.org> > Reviewed-by: Heiko Stuebner <heiko@sntech.de> Oops, I applied the old one too quickly. I've replaced the V1 patch in the clk tree with this version. Thanks Doug for pointing that out. Regards, Mike > --- > > Changes in v3: None > Changes in v2: > - split into two patches of add clock node in PD_VIDEO and > use new defined clock ID > > drivers/clk/rockchip/clk-rk3288.c | 68 +++++++++++++++++++-------------------- > 1 file changed, 34 insertions(+), 34 deletions(-) > > diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c > index a58b0b3..dd204cb 100644 > --- a/drivers/clk/rockchip/clk-rk3288.c > +++ b/drivers/clk/rockchip/clk-rk3288.c > @@ -219,12 +219,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS), > DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0, > RK3288_CLKSEL_CON(1), 0, 3, DFLAGS), > - GATE(0, "aclk_cpu", "aclk_cpu_pre", 0, > + GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, > RK3288_CLKGATE_CON(0), 3, GFLAGS), > - COMPOSITE_NOMUX(0, "pclk_cpu", "aclk_cpu_pre", 0, > + COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0, > RK3288_CLKSEL_CON(1), 12, 3, DFLAGS, > RK3288_CLKGATE_CON(0), 5, GFLAGS), > - COMPOSITE_NOMUX_DIVTBL(0, "hclk_cpu", "aclk_cpu_pre", 0, > + COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0, > RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t, > RK3288_CLKGATE_CON(0), 4, GFLAGS), > GATE(0, "c2c_host", "aclk_cpu_src", 0, > @@ -309,7 +309,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0, > RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS, > RK3288_CLKGATE_CON(3), 5, GFLAGS), > - COMPOSITE(0, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0, > + COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0, > RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, > RK3288_CLKGATE_CON(3), 4, GFLAGS), > > @@ -320,35 +320,35 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS, > RK3288_CLKGATE_CON(3), 3, GFLAGS), > > - COMPOSITE_NODIV(0, "sclk_edp_24m", mux_edp_24m_p, 0, > + COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0, > RK3288_CLKSEL_CON(28), 15, 1, MFLAGS, > RK3288_CLKGATE_CON(3), 12, GFLAGS), > - COMPOSITE(0, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0, > + COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0, > RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS, > RK3288_CLKGATE_CON(3), 13, GFLAGS), > > - COMPOSITE(0, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0, > + COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0, > RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS, > RK3288_CLKGATE_CON(3), 14, GFLAGS), > - COMPOSITE(0, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0, > + COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0, > RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS, > RK3288_CLKGATE_CON(3), 15, GFLAGS), > > - GATE(0, "sclk_hdmi_hdcp", "xin24m", 0, > + GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, > RK3288_CLKGATE_CON(5), 12, GFLAGS), > - GATE(0, "sclk_hdmi_cec", "xin32k", 0, > + GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0, > RK3288_CLKGATE_CON(5), 11, GFLAGS), > > - COMPOSITE(0, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0, > + COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0, > RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS, > RK3288_CLKGATE_CON(13), 13, GFLAGS), > - DIV(0, "hclk_hevc", "aclk_hevc", 0, > + DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0, > RK3288_CLKSEL_CON(40), 12, 2, DFLAGS), > > - COMPOSITE(0, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0, > + COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0, > RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, > RK3288_CLKGATE_CON(13), 14, GFLAGS), > - COMPOSITE(0, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0, > + COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0, > RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, > RK3288_CLKGATE_CON(13), 15, GFLAGS), > > @@ -371,13 +371,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0, > RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, > RK3288_CLKGATE_CON(2), 0, GFLAGS), > - COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_src", 0, > + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, > RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, > RK3288_CLKGATE_CON(2), 3, GFLAGS), > - COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_src", 0, > + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, > RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, > RK3288_CLKGATE_CON(2), 2, GFLAGS), > - GATE(0, "aclk_peri", "aclk_peri_src", 0, > + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, > RK3288_CLKGATE_CON(2), 1, GFLAGS), > > /* > @@ -643,34 +643,34 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS), > GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS), > GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS), > - GATE(0, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS), > - GATE(0, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS), > - GATE(0, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS), > + GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS), > + GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS), > + GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS), > GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS), > GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS), > - GATE(0, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS), > - GATE(0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS), > - GATE(0, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS), > - GATE(0, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS), > - GATE(0, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS), > - GATE(0, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS), > - GATE(0, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS), > - GATE(0, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS), > + GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS), > + GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS), > + GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS), > + GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS), > + GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS), > + GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS), > + GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS), > + GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS), > > /* aclk_vio0 gates */ > GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS), > - GATE(0, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS), > - GATE(0, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS), > - GATE(0, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS), > + GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS), > + GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS), > + GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS), > > /* aclk_vio1 gates */ > GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS), > - GATE(0, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS), > - GATE(0, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS), > + GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS), > + GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS), > > /* aclk_rga_pre gates */ > GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS), > - GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS), > + GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS), > > /* > * Other ungrouped clocks. > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 3/3] clk: rockchip: add clock node in PD_VIDEO 2014-09-25 7:48 ` Kever Yang @ 2014-09-25 7:48 ` Kever Yang -1 siblings, 0 replies; 15+ messages in thread From: Kever Yang @ 2014-09-25 7:48 UTC (permalink / raw) To: linux-arm-kernel This patch add the clock node in PD_VIDEO Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> --- Changes in v3: - add a fix factor - introduce a virtual node to implement the clock struct Changes in v2: - split out the patch drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index dd204cb..d466814 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -296,6 +296,20 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 11, GFLAGS), + /* + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system, + * so we ignore the mux and make clocks nodes as following, + */ + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, + RK3288_CLKGATE_CON(9), 0, GFLAGS), + /* + * We introduce a virtul node of hclk_vodec_pre_v to split one clock + * sturct with a gate and a fix divider into two node in software. + */ + GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0, + RK3288_CLKGATE_CON(3), 10, GFLAGS), + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, + RK3288_CLKGATE_CON(9), 1, GFLAGS), COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS, @@ -711,6 +725,12 @@ static void __init rk3288_clk_init(struct device_node *np) pr_warn("%s: could not register clock usb480m: %ld\n", __func__, PTR_ERR(clk)); + clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre", + "hclk_vcodec_pre_v", 0, 1, 4); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", + __func__, PTR_ERR(clk)); + rockchip_clk_register_plls(rk3288_pll_clks, ARRAY_SIZE(rk3288_pll_clks), RK3288_GRF_SOC_STATUS); -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 3/3] clk: rockchip: add clock node in PD_VIDEO @ 2014-09-25 7:48 ` Kever Yang 0 siblings, 0 replies; 15+ messages in thread From: Kever Yang @ 2014-09-25 7:48 UTC (permalink / raw) To: heiko, Mike Turquette Cc: dianders, sonnyrao, addy.ke, cf, xjq, hj, huangtao, linux-rockchip, Kever Yang, linux-arm-kernel, linux-kernel This patch add the clock node in PD_VIDEO Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> --- Changes in v3: - add a fix factor - introduce a virtual node to implement the clock struct Changes in v2: - split out the patch drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index dd204cb..d466814 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -296,6 +296,20 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 11, GFLAGS), + /* + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system, + * so we ignore the mux and make clocks nodes as following, + */ + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, + RK3288_CLKGATE_CON(9), 0, GFLAGS), + /* + * We introduce a virtul node of hclk_vodec_pre_v to split one clock + * sturct with a gate and a fix divider into two node in software. + */ + GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0, + RK3288_CLKGATE_CON(3), 10, GFLAGS), + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, + RK3288_CLKGATE_CON(9), 1, GFLAGS), COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS, @@ -711,6 +725,12 @@ static void __init rk3288_clk_init(struct device_node *np) pr_warn("%s: could not register clock usb480m: %ld\n", __func__, PTR_ERR(clk)); + clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre", + "hclk_vcodec_pre_v", 0, 1, 4); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", + __func__, PTR_ERR(clk)); + rockchip_clk_register_plls(rk3288_pll_clks, ARRAY_SIZE(rk3288_pll_clks), RK3288_GRF_SOC_STATUS); -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 3/3] clk: rockchip: add clock node in PD_VIDEO 2014-09-25 7:48 ` Kever Yang @ 2014-09-25 22:24 ` Doug Anderson -1 siblings, 0 replies; 15+ messages in thread From: Doug Anderson @ 2014-09-25 22:24 UTC (permalink / raw) To: linux-arm-kernel Kever, On Thu, Sep 25, 2014 at 12:48 AM, Kever Yang <kever.yang@rock-chips.com> wrote: > This patch add the clock node in PD_VIDEO > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > --- > > Changes in v3: > - add a fix factor > - introduce a virtual node to implement the clock struct > > Changes in v2: > - split out the patch > > drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c > index dd204cb..d466814 100644 > --- a/drivers/clk/rockchip/clk-rk3288.c > +++ b/drivers/clk/rockchip/clk-rk3288.c > @@ -296,6 +296,20 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, > RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, > RK3288_CLKGATE_CON(3), 11, GFLAGS), > + /* > + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system, > + * so we ignore the mux and make clocks nodes as following, > + */ > + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, > + RK3288_CLKGATE_CON(9), 0, GFLAGS), > + /* > + * We introduce a virtul node of hclk_vodec_pre_v to split one clock > + * sturct with a gate and a fix divider into two node in software. nit: s/sturct/struct ...I think Mike will fix this up when applying. > + */ > + GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0, > + RK3288_CLKGATE_CON(3), 10, GFLAGS), > + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, > + RK3288_CLKGATE_CON(9), 1, GFLAGS), > > COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0, > RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS, > @@ -711,6 +725,12 @@ static void __init rk3288_clk_init(struct device_node *np) > pr_warn("%s: could not register clock usb480m: %ld\n", > __func__, PTR_ERR(clk)); > > + clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre", > + "hclk_vcodec_pre_v", 0, 1, 4); > + if (IS_ERR(clk)) > + pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", > + __func__, PTR_ERR(clk)); > + > rockchip_clk_register_plls(rk3288_pll_clks, > ARRAY_SIZE(rk3288_pll_clks), > RK3288_GRF_SOC_STATUS); Looks reasonable. Reviewed-by: Doug Anderson <dianders@chromium.org> I've booted this up and the new clocks show up and have the right parents. Tested-by: Doug Anderson <dianders@chromium.org> ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 3/3] clk: rockchip: add clock node in PD_VIDEO @ 2014-09-25 22:24 ` Doug Anderson 0 siblings, 0 replies; 15+ messages in thread From: Doug Anderson @ 2014-09-25 22:24 UTC (permalink / raw) To: Kever Yang Cc: Heiko Stübner, Mike Turquette, Sonny Rao, Addy Ke, Eddie Cai, Jianqun Xu, han jiang, Tao Huang, linux-rockchip, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Kever, On Thu, Sep 25, 2014 at 12:48 AM, Kever Yang <kever.yang@rock-chips.com> wrote: > This patch add the clock node in PD_VIDEO > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > --- > > Changes in v3: > - add a fix factor > - introduce a virtual node to implement the clock struct > > Changes in v2: > - split out the patch > > drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c > index dd204cb..d466814 100644 > --- a/drivers/clk/rockchip/clk-rk3288.c > +++ b/drivers/clk/rockchip/clk-rk3288.c > @@ -296,6 +296,20 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, > RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, > RK3288_CLKGATE_CON(3), 11, GFLAGS), > + /* > + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system, > + * so we ignore the mux and make clocks nodes as following, > + */ > + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, > + RK3288_CLKGATE_CON(9), 0, GFLAGS), > + /* > + * We introduce a virtul node of hclk_vodec_pre_v to split one clock > + * sturct with a gate and a fix divider into two node in software. nit: s/sturct/struct ...I think Mike will fix this up when applying. > + */ > + GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0, > + RK3288_CLKGATE_CON(3), 10, GFLAGS), > + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, > + RK3288_CLKGATE_CON(9), 1, GFLAGS), > > COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0, > RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS, > @@ -711,6 +725,12 @@ static void __init rk3288_clk_init(struct device_node *np) > pr_warn("%s: could not register clock usb480m: %ld\n", > __func__, PTR_ERR(clk)); > > + clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre", > + "hclk_vcodec_pre_v", 0, 1, 4); > + if (IS_ERR(clk)) > + pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", > + __func__, PTR_ERR(clk)); > + > rockchip_clk_register_plls(rk3288_pll_clks, > ARRAY_SIZE(rk3288_pll_clks), > RK3288_GRF_SOC_STATUS); Looks reasonable. Reviewed-by: Doug Anderson <dianders@chromium.org> I've booted this up and the new clocks show up and have the right parents. Tested-by: Doug Anderson <dianders@chromium.org> ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 3/3] clk: rockchip: add clock node in PD_VIDEO 2014-09-25 22:24 ` Doug Anderson @ 2014-09-25 22:48 ` Mike Turquette -1 siblings, 0 replies; 15+ messages in thread From: Mike Turquette @ 2014-09-25 22:48 UTC (permalink / raw) To: linux-arm-kernel Quoting Doug Anderson (2014-09-25 15:24:22) > Kever, > > On Thu, Sep 25, 2014 at 12:48 AM, Kever Yang <kever.yang@rock-chips.com> wrote: > > This patch add the clock node in PD_VIDEO > > > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > > --- > > > > Changes in v3: > > - add a fix factor > > - introduce a virtual node to implement the clock struct > > > > Changes in v2: > > - split out the patch > > > > drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++++ > > 1 file changed, 20 insertions(+) > > > > diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c > > index dd204cb..d466814 100644 > > --- a/drivers/clk/rockchip/clk-rk3288.c > > +++ b/drivers/clk/rockchip/clk-rk3288.c > > @@ -296,6 +296,20 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > > COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, > > RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, > > RK3288_CLKGATE_CON(3), 11, GFLAGS), > > + /* > > + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system, > > + * so we ignore the mux and make clocks nodes as following, > > + */ > > + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, > > + RK3288_CLKGATE_CON(9), 0, GFLAGS), > > + /* > > + * We introduce a virtul node of hclk_vodec_pre_v to split one clock > > + * sturct with a gate and a fix divider into two node in software. > > nit: s/sturct/struct > > ...I think Mike will fix this up when applying. Fixed locally. > > > + */ > > + GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0, > > + RK3288_CLKGATE_CON(3), 10, GFLAGS), > > + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, > > + RK3288_CLKGATE_CON(9), 1, GFLAGS), > > > > COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0, > > RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS, > > @@ -711,6 +725,12 @@ static void __init rk3288_clk_init(struct device_node *np) > > pr_warn("%s: could not register clock usb480m: %ld\n", > > __func__, PTR_ERR(clk)); > > > > + clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre", > > + "hclk_vcodec_pre_v", 0, 1, 4); > > + if (IS_ERR(clk)) > > + pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", > > + __func__, PTR_ERR(clk)); > > + > > rockchip_clk_register_plls(rk3288_pll_clks, > > ARRAY_SIZE(rk3288_pll_clks), > > RK3288_GRF_SOC_STATUS); > > Looks reasonable. > > Reviewed-by: Doug Anderson <dianders@chromium.org> > > I've booted this up and the new clocks show up and have the right parents. > > Tested-by: Doug Anderson <dianders@chromium.org> Applied to clk-next. Thanks, Mike ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 3/3] clk: rockchip: add clock node in PD_VIDEO @ 2014-09-25 22:48 ` Mike Turquette 0 siblings, 0 replies; 15+ messages in thread From: Mike Turquette @ 2014-09-25 22:48 UTC (permalink / raw) To: Doug Anderson, Kever Yang Cc: Heiko Stübner, Sonny Rao, Addy Ke, Eddie Cai, Jianqun Xu, han jiang, Tao Huang, linux-rockchip, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Quoting Doug Anderson (2014-09-25 15:24:22) > Kever, > > On Thu, Sep 25, 2014 at 12:48 AM, Kever Yang <kever.yang@rock-chips.com> wrote: > > This patch add the clock node in PD_VIDEO > > > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > > --- > > > > Changes in v3: > > - add a fix factor > > - introduce a virtual node to implement the clock struct > > > > Changes in v2: > > - split out the patch > > > > drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++++ > > 1 file changed, 20 insertions(+) > > > > diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c > > index dd204cb..d466814 100644 > > --- a/drivers/clk/rockchip/clk-rk3288.c > > +++ b/drivers/clk/rockchip/clk-rk3288.c > > @@ -296,6 +296,20 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > > COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, > > RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, > > RK3288_CLKGATE_CON(3), 11, GFLAGS), > > + /* > > + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system, > > + * so we ignore the mux and make clocks nodes as following, > > + */ > > + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, > > + RK3288_CLKGATE_CON(9), 0, GFLAGS), > > + /* > > + * We introduce a virtul node of hclk_vodec_pre_v to split one clock > > + * sturct with a gate and a fix divider into two node in software. > > nit: s/sturct/struct > > ...I think Mike will fix this up when applying. Fixed locally. > > > + */ > > + GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0, > > + RK3288_CLKGATE_CON(3), 10, GFLAGS), > > + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, > > + RK3288_CLKGATE_CON(9), 1, GFLAGS), > > > > COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0, > > RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS, > > @@ -711,6 +725,12 @@ static void __init rk3288_clk_init(struct device_node *np) > > pr_warn("%s: could not register clock usb480m: %ld\n", > > __func__, PTR_ERR(clk)); > > > > + clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre", > > + "hclk_vcodec_pre_v", 0, 1, 4); > > + if (IS_ERR(clk)) > > + pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", > > + __func__, PTR_ERR(clk)); > > + > > rockchip_clk_register_plls(rk3288_pll_clks, > > ARRAY_SIZE(rk3288_pll_clks), > > RK3288_GRF_SOC_STATUS); > > Looks reasonable. > > Reviewed-by: Doug Anderson <dianders@chromium.org> > > I've booted this up and the new clocks show up and have the right parents. > > Tested-by: Doug Anderson <dianders@chromium.org> Applied to clk-next. Thanks, Mike ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2014-09-25 22:48 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
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2014-09-25 7:48 [PATCH v3 0/3] Add clock binding id for rk3288 Kever Yang
2014-09-25 7:48 ` Kever Yang
2014-09-25 7:48 ` [PATCH v3 1/3] clk: rockchip: add some needed " Kever Yang
[not found] ` <1411631328-14973-2-git-send-email-kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2014-09-25 22:07 ` Mike Turquette
2014-09-25 22:07 ` Mike Turquette
2014-09-25 7:48 ` [PATCH v3 2/3] clk: rockchip: use the clock id for nodes init Kever Yang
2014-09-25 7:48 ` Kever Yang
2014-09-25 22:06 ` Mike Turquette
2014-09-25 22:06 ` Mike Turquette
2014-09-25 7:48 ` [PATCH v3 3/3] clk: rockchip: add clock node in PD_VIDEO Kever Yang
2014-09-25 7:48 ` Kever Yang
2014-09-25 22:24 ` Doug Anderson
2014-09-25 22:24 ` Doug Anderson
2014-09-25 22:48 ` Mike Turquette
2014-09-25 22:48 ` Mike Turquette
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