From: Daniel Vetter <daniel@ffwll.ch>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/5] drm/i915: Fix chv PCS DW11 register defines
Date: Tue, 21 Oct 2014 18:08:26 +0200 [thread overview]
Message-ID: <20141021160826.GA26941@phenom.ffwll.local> (raw)
In-Reply-To: <871tq7m5bd.fsf@intel.com>
On Fri, Oct 17, 2014 at 12:08:38PM +0300, Jani Nikula wrote:
> On Thu, 16 Oct 2014, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > I managed to fumble the per spline PCS DW11 register defines in:
> > commit 9d4f193b077c1973add53e40ff9410a3371900af
>
> Looks like commit 570e2a747bc06cd8620662c5125ec2dc964c511b in my repo.
Fixed.
>
> > Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Date: Thu Jun 26 13:47:19 2014 +0300
> >
> > drm/i915: Clear TX FIFO reset master override bits on chv
> >
> > Fortunately the bit in DW0 that was cleared due to this didn't have
> > any effect as long as the bit we meant to clear was already zero.
>
> I did not have a spec handy, so I didn't check the regs, but clearly the
> DW11 macro referencing other DW11 macros instead of DW0 makes sense.
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Merged this and patch 1 to dinq, patch 2 indeed looks a bit more like
-fixes material.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2014-10-21 16:08 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-16 17:52 [PATCH 0/5] drm/i915: Random pile of VLV/CHV fixes ville.syrjala
2014-10-16 17:52 ` [PATCH 1/5] drm/i915: Don't claim that we're resetting PCH ADPA register ville.syrjala
2014-10-17 8:50 ` Jani Nikula
2014-10-16 17:52 ` [PATCH 2/5] drm/i915: Fix GMBUSFREQ on vlv/chv ville.syrjala
2014-10-17 8:59 ` Jani Nikula
2014-10-17 9:00 ` Jani Nikula
2014-10-22 13:41 ` Jani Nikula
2014-10-16 17:52 ` [PATCH 3/5] drm/i915: Fix chv PCS DW11 register defines ville.syrjala
2014-10-17 9:08 ` Jani Nikula
2014-10-21 16:08 ` Daniel Vetter [this message]
2014-10-16 17:52 ` [PATCH 4/5] drm/i915: Do vlv cmnlane toggle w/a in more cases ville.syrjala
2014-10-28 17:57 ` Jesse Barnes
2014-10-28 18:12 ` Ville Syrjälä
2014-11-03 11:10 ` Daniel Vetter
2014-10-16 17:52 ` [PATCH 5/5] drm/i915: Initialize new chv primary plane and pipe blender registers ville.syrjala
2014-10-29 21:18 ` Rodrigo Vivi
2014-10-30 8:33 ` Ville Syrjälä
2014-10-30 19:14 ` Rodrigo Vivi
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