All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jani Nikula <jani.nikula@linux.intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/5] drm/i915: Don't claim that we're resetting	PCH ADPA register
Date: Fri, 17 Oct 2014 11:50:43 +0300	[thread overview]
Message-ID: <87a94vm658.fsf@intel.com> (raw)
In-Reply-To: <1413481954-18622-2-git-send-email-ville.syrjala@linux.intel.com>

On Thu, 16 Oct 2014, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_crt_reset() resets the ADPA register on all gen5+ platforms.
> However the debug message claims it's touching the PCH ADPA register
> which is clearly not what it does on VLV. Drop the PCH part from
> the debug message.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_crt.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index dacaad5..a9af9a4 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -775,7 +775,7 @@ static void intel_crt_reset(struct drm_connector *connector)
>  		I915_WRITE(crt->adpa_reg, adpa);
>  		POSTING_READ(crt->adpa_reg);
>  
> -		DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
> +		DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
>  		crt->force_hotplug_required = 1;
>  	}
>  
> -- 
> 2.0.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2014-10-17  8:51 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-10-16 17:52 [PATCH 0/5] drm/i915: Random pile of VLV/CHV fixes ville.syrjala
2014-10-16 17:52 ` [PATCH 1/5] drm/i915: Don't claim that we're resetting PCH ADPA register ville.syrjala
2014-10-17  8:50   ` Jani Nikula [this message]
2014-10-16 17:52 ` [PATCH 2/5] drm/i915: Fix GMBUSFREQ on vlv/chv ville.syrjala
2014-10-17  8:59   ` Jani Nikula
2014-10-17  9:00   ` Jani Nikula
2014-10-22 13:41     ` Jani Nikula
2014-10-16 17:52 ` [PATCH 3/5] drm/i915: Fix chv PCS DW11 register defines ville.syrjala
2014-10-17  9:08   ` Jani Nikula
2014-10-21 16:08     ` Daniel Vetter
2014-10-16 17:52 ` [PATCH 4/5] drm/i915: Do vlv cmnlane toggle w/a in more cases ville.syrjala
2014-10-28 17:57   ` Jesse Barnes
2014-10-28 18:12     ` Ville Syrjälä
2014-11-03 11:10       ` Daniel Vetter
2014-10-16 17:52 ` [PATCH 5/5] drm/i915: Initialize new chv primary plane and pipe blender registers ville.syrjala
2014-10-29 21:18   ` Rodrigo Vivi
2014-10-30  8:33     ` Ville Syrjälä
2014-10-30 19:14       ` Rodrigo Vivi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87a94vm658.fsf@intel.com \
    --to=jani.nikula@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=ville.syrjala@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.