All of lore.kernel.org
 help / color / mirror / Atom feed
From: Ralf Baechle <ralf@linux-mips.org>
To: "Steven J. Hill" <Steven.Hill@imgtec.com>,
	Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH 05/11] MIPS: mm: c-r4k: Ensure CCA is set to non-coherent on UP kernels.
Date: Thu, 13 Nov 2014 11:31:08 +0100	[thread overview]
Message-ID: <20141113103108.GB13753@linux-mips.org> (raw)
In-Reply-To: <1415858743-24492-6-git-send-email-Steven.Hill@imgtec.com>

On Thu, Nov 13, 2014 at 12:05:37AM -0600, Steven J. Hill wrote:

> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 1559360..076e660 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -1595,8 +1595,17 @@ early_param("cca", cca_setup);
>  
>  static void coherency_setup(void)
>  {
> -	if (cca < 0 || cca > 7)
> -		cca = read_c0_config() & CONF_CM_CMASK;
> +	if (cca < 0 || cca > 7) {
> +		/*
> +		 * Set CCA to non-coherent to ensure that the UP kernel
> +		 * behaves properly even on MC processors where the ROM
> +		 * may have prepared the C0 registers for SMP operation.
> +		 */
> +		if (!config_enabled(CONFIG_SMP))
> +			cca = _CACHE_CACHABLE_NONCOHERENT >> _CACHE_SHIFT;
> +		else
> +			cca = read_c0_config() & CONF_CM_CMASK;
> +	}

NAK.  This would trigger falsely on pretty much every SMP platform in
MIPS history except Octeon - with usually fatal consequences.

Is there a performance disadvantage or why is this desirable?

  Ralf

  reply	other threads:[~2014-11-13 10:31 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-13  6:05 [PATCH 00/11] Add support for eXtended Physical Addressing Steven J. Hill
2014-11-13  6:05 ` [PATCH 01/11] MIPS: HIGHMEM fixes for cache aliasing and non-DMA I/O Steven J. Hill
2014-11-13  6:05 ` [PATCH 02/11] MIPS: Revert fixrange_init() limiting to the FIXMAP region Steven J. Hill
2014-11-13 11:13   ` Ralf Baechle
2014-11-13  6:05 ` [PATCH 03/11] MIPS: Rearrange PTE bits into fixed positions for MIPS R2 Steven J. Hill
2014-11-13  6:05 ` [PATCH 04/11] MIPS: Removal of execute bit in page tables for HEAP/BSS Steven J. Hill
2014-11-13 11:36   ` Ralf Baechle
2014-11-13  6:05 ` [PATCH 05/11] MIPS: mm: c-r4k: Ensure CCA is set to non-coherent on UP kernels Steven J. Hill
2014-11-13 10:31   ` Ralf Baechle [this message]
2014-11-13  6:05 ` [PATCH 06/11] MIPS: Add CP0 macros for extended EntryLo registers Steven J. Hill
2014-11-13 12:25   ` Sergei Shtylyov
2014-11-13  6:05 ` [PATCH 07/11] MIPS: Fix address type used for early memory detection Steven J. Hill
2014-11-13  6:05 ` [PATCH 08/11] MIPS: Cosmetic cleanups of page table headers Steven J. Hill
2014-11-13  6:05 ` [PATCH 09/11] MIPS: Add MFHC0 and MTHC0 instructions to uasm Steven J. Hill
2014-11-13  6:05 ` [PATCH 10/11] MIPS: Add support for XPA Steven J. Hill
2014-11-13  6:05 ` [PATCH 11/11] MIPS: XPA: Add new configuration file Steven J. Hill
2014-11-13  6:21 ` [PATCH 00/11] Add support for eXtended Physical Addressing Ralf Baechle

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20141113103108.GB13753@linux-mips.org \
    --to=ralf@linux-mips.org \
    --cc=Steven.Hill@imgtec.com \
    --cc=linux-mips@linux-mips.org \
    --cc=markos.chandras@imgtec.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.