From: Matt Fleming <matt@console-pimps.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Vikas Shivappa <vikas.shivappa@linux.intel.com>,
linux-kernel@vger.kernel.org, vikas.shivappa@intel.com,
hpa@zytor.com, mingo@kernel.org, tj@kernel.org,
matt.fleming@intel.com, will.auld@intel.com,
peterz@infradead.org
Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support
Date: Sun, 23 Nov 2014 19:26:13 +0000 [thread overview]
Message-ID: <20141123192613.GA2956@console-pimps.org> (raw)
In-Reply-To: <alpine.DEB.2.11.1411211224070.6439@nanos>
On Fri, 21 Nov, at 03:19:52PM, Thomas Gleixner wrote:
> > + barrier();
> > + cqe_genable = true;
>
> What's the exact point of that barrier?
Yes, this definitely needs documenting. Vikas?
> > +
> > +/*
> > + * Tests if only contiguous bits are set.
> > + */
> > +
> > +static inline bool cbm_iscontiguous(unsigned long var)
> > +{
>
> This one here can be implemented with existing bitmap functions as
> well.
Something like this?
first_bit = find_next_bit(map, nr_bits, -1);
zero_bit = find_next_zero_bit(map, nr_bits, first_bit);
if (find_next_bit(map, nr_bits, zero_bit) < nr_bits)
return -EINVAL; /* non-contiguous bits */
--
Matt Fleming, Intel Open Source Technology Center
next prev parent reply other threads:[~2014-11-23 19:26 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-20 1:05 [PATCH] x86: Intel Cache Allocation Technology support Vikas Shivappa
2014-11-21 14:19 ` Thomas Gleixner
2014-11-21 20:00 ` Vikas Shivappa
2014-11-21 20:15 ` Borislav Petkov
2014-11-21 21:14 ` Vikas Shivappa
2014-11-23 20:04 ` Thomas Gleixner
2014-11-24 9:36 ` Shivappa, Vikas
2014-11-23 19:26 ` Matt Fleming [this message]
2014-11-23 19:29 ` Thomas Gleixner
2014-11-24 9:44 ` Shivappa, Vikas
2014-11-26 0:01 ` Shivappa, Vikas
2014-11-26 0:05 ` Shivappa, Vikas
2014-11-21 20:29 ` Dave Hansen
2014-11-21 20:43 ` Thomas Gleixner
2014-11-21 21:27 ` Vikas Shivappa
2014-11-21 21:25 ` Vikas Shivappa
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