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From: Dave Hansen <dave.hansen@intel.com>
To: Vikas Shivappa <vikas.shivappa@linux.intel.com>,
	linux-kernel@vger.kernel.org
Cc: vikas.shivappa@intel.com, hpa@zytor.com, tglx@linutronix.de,
	mingo@kernel.org, tj@kernel.org, matt.flemming@intel.com,
	will.auld@intel.com, peterz@infradead.org
Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support
Date: Fri, 21 Nov 2014 12:29:56 -0800	[thread overview]
Message-ID: <546FA0C4.1000402@intel.com> (raw)
In-Reply-To: <1416445539-24856-1-git-send-email-vikas.shivappa@linux.intel.com>

On 11/19/2014 05:05 PM, Vikas Shivappa wrote:
> +	/*
> +	 * Hard code the checks and values for HSW SKUs.
> +	 * Unfortunately! have to check against only these brand name strings.
> +	 */
> +
> +	for (i = 0; i < 5; i++)
> +		if (!strcmp(hsw_brandstrs[i], c->x86_model_id)) {
> +			c->x86_cqe_closs = 4;
> +			c->x86_cqe_cbmlength = 20;
> +			return true;
> +		}

Please use ARRAY_SIZE() here.  Otherwise, I guarantee the next string
you add to hsw_brandstrs[] gets silently ignored.

Are there really only 5 CPUs?  This:

> http://ark.intel.com/products/family/78583/Intel-Xeon-Processor-E5-v3-Family#@Server

lists 32 skus.

  parent reply	other threads:[~2014-11-21 20:29 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-20  1:05 [PATCH] x86: Intel Cache Allocation Technology support Vikas Shivappa
2014-11-21 14:19 ` Thomas Gleixner
2014-11-21 20:00   ` Vikas Shivappa
2014-11-21 20:15     ` Borislav Petkov
2014-11-21 21:14       ` Vikas Shivappa
2014-11-23 20:04     ` Thomas Gleixner
2014-11-24  9:36       ` Shivappa, Vikas
2014-11-23 19:26   ` Matt Fleming
2014-11-23 19:29     ` Thomas Gleixner
2014-11-24  9:44   ` Shivappa, Vikas
2014-11-26  0:01   ` Shivappa, Vikas
2014-11-26  0:05   ` Shivappa, Vikas
2014-11-21 20:29 ` Dave Hansen [this message]
2014-11-21 20:43   ` Thomas Gleixner
2014-11-21 21:27     ` Vikas Shivappa
2014-11-21 21:25 ` Vikas Shivappa

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