From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: Query: ARM64: Behavior of el1_dbg exception while executing el0_dbg
Date: Fri, 16 Jan 2015 16:22:44 +0000 [thread overview]
Message-ID: <20150116162244.GA7091@arm.com> (raw)
In-Reply-To: <54B8FD49.2060503@redhat.com>
On Fri, Jan 16, 2015 at 12:00:09PM +0000, Pratyush Anand wrote:
> On Thursday 15 January 2015 10:17 PM, Pratyush Anand wrote:
> > On Tuesday 13 January 2015 11:23 PM, Pratyush Anand wrote:
> >> I will still try to find some way to capture enable_dbg macro path.H
> >
> > I did instrumented debug tap points at all the location from where
> > enable_debug macro is called(see attached debug patch). But, I do not
> > see that, execution reaches to any of those tap points between el0_dbg
> > and el1_dbg, and tap points debug log also confirms that el1_dbg is
> > raised before el0_dbg is returned.
>
> Probably we all missed this, ARMv8 specs is very clear about it. In
> section "D2.1 About debug exceptions" it says:
>
> Software Breakpoint Instruction exceptions cannot be masked. The PE
> takes Software Breakpoint Instruction exceptions regardless of both of
> the following:
> ? The current Exception level.
> ? The current Security state.
Ah, of course, I completely forgot you were using software breakpoints!
> So, reception of el1_dbg while executing el0_dbg seems perfectly normal
> to me. If you agree then I am back with the original query which I asked
> in the beginning of the
> thread,(http://permalink.gmane.org/gmane.linux.ports.arm.kernel/383672)
> ie how can instruction_pointer be wrong when second el1_dbg is called
> recursively(as follows).
>
> [1]-> el0_dbg (After executing BRK instruction by user)
> [2] -> el1_dbg (when uprobe break handler at [1] executes BRK instruction)
> (At the end of this ELR_EL1 is programmed with fffffdfffc000004)
> [3] -> el1_dbg (when kprobe break handler at [2] enables single stepping)
> (Here ELR_EL1 was found fffffe0000092470).So When this el1_dbg was
> received, then regs->pc values are not same what was programmed in
> ELR_EL1 at the return of [2].
Perhaps you're not removing the BRK instruction properly, and so you try to
single-step a trapping instruction and end up stepping into the exception?
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Pratyush Anand <panand@redhat.com>
Cc: Catalin Marinas <Catalin.Marinas@arm.com>,
Steve Capper <steve.capper@linaro.org>,
Oleg Nesterov <oleg@redhat.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
David Long <dave.long@linaro.org>,
William Cohen <wcohen@redhat.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: Query: ARM64: Behavior of el1_dbg exception while executing el0_dbg
Date: Fri, 16 Jan 2015 16:22:44 +0000 [thread overview]
Message-ID: <20150116162244.GA7091@arm.com> (raw)
In-Reply-To: <54B8FD49.2060503@redhat.com>
On Fri, Jan 16, 2015 at 12:00:09PM +0000, Pratyush Anand wrote:
> On Thursday 15 January 2015 10:17 PM, Pratyush Anand wrote:
> > On Tuesday 13 January 2015 11:23 PM, Pratyush Anand wrote:
> >> I will still try to find some way to capture enable_dbg macro path.H
> >
> > I did instrumented debug tap points at all the location from where
> > enable_debug macro is called(see attached debug patch). But, I do not
> > see that, execution reaches to any of those tap points between el0_dbg
> > and el1_dbg, and tap points debug log also confirms that el1_dbg is
> > raised before el0_dbg is returned.
>
> Probably we all missed this, ARMv8 specs is very clear about it. In
> section "D2.1 About debug exceptions" it says:
>
> Software Breakpoint Instruction exceptions cannot be masked. The PE
> takes Software Breakpoint Instruction exceptions regardless of both of
> the following:
> • The current Exception level.
> • The current Security state.
Ah, of course, I completely forgot you were using software breakpoints!
> So, reception of el1_dbg while executing el0_dbg seems perfectly normal
> to me. If you agree then I am back with the original query which I asked
> in the beginning of the
> thread,(http://permalink.gmane.org/gmane.linux.ports.arm.kernel/383672)
> ie how can instruction_pointer be wrong when second el1_dbg is called
> recursively(as follows).
>
> [1]-> el0_dbg (After executing BRK instruction by user)
> [2] -> el1_dbg (when uprobe break handler at [1] executes BRK instruction)
> (At the end of this ELR_EL1 is programmed with fffffdfffc000004)
> [3] -> el1_dbg (when kprobe break handler at [2] enables single stepping)
> (Here ELR_EL1 was found fffffe0000092470).So When this el1_dbg was
> received, then regs->pc values are not same what was programmed in
> ELR_EL1 at the return of [2].
Perhaps you're not removing the BRK instruction properly, and so you try to
single-step a trapping instruction and end up stepping into the exception?
Will
next prev parent reply other threads:[~2015-01-16 16:22 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-08 13:15 Query: ARM64: Behavior of el1_dbg exception while executing el0_dbg Pratyush Anand
2015-01-08 15:49 ` William Cohen
2015-01-08 17:19 ` Pratyush Anand
2015-01-08 16:23 ` Will Deacon
2015-01-08 17:28 ` Pratyush Anand
2015-01-09 15:46 ` Will Deacon
2015-01-09 17:13 ` Pratyush Anand
2015-01-09 17:13 ` Pratyush Anand
2015-01-12 17:30 ` Will Deacon
2015-01-12 17:30 ` Will Deacon
2015-01-12 19:25 ` William Cohen
2015-01-12 19:25 ` William Cohen
2015-01-13 6:46 ` Pratyush Anand
2015-01-13 6:46 ` Pratyush Anand
2015-01-13 15:52 ` Catalin Marinas
2015-01-13 15:52 ` Catalin Marinas
2015-01-13 17:53 ` Pratyush Anand
2015-01-13 17:53 ` Pratyush Anand
2015-01-15 16:47 ` Pratyush Anand
2015-01-15 16:47 ` Pratyush Anand
2015-01-16 12:00 ` Pratyush Anand
2015-01-16 12:00 ` Pratyush Anand
2015-01-16 14:55 ` Pratyush Anand
2015-01-16 14:55 ` Pratyush Anand
2015-01-16 16:22 ` Will Deacon [this message]
2015-01-16 16:22 ` Will Deacon
2015-01-19 6:10 ` Pratyush Anand
2015-01-19 6:10 ` Pratyush Anand
2015-01-19 10:11 ` Will Deacon
2015-01-19 10:11 ` Will Deacon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150116162244.GA7091@arm.com \
--to=will.deacon@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.