[PATCH 1/2] clock: redefine variable clocks_per_pll as a struct member

[PATCH 1/2] clock: redefine variable clocks_per_pll as a struct member

[Yuantian.Tang]

From: Tang Yuantian <Yuantian.Tang@freescale.com>

redefine variable clocks_per_pll as a struct member

If there are multiple PLL clock nodes, this variable will
get overwritten. Redefining it as a struct member can avoid that.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
These patches are based on following three patches which are acked
by Scott wood <scottwood@freescale.com>:
	1. http://patchwork.ozlabs.org/patch/417292/
		Revert "clk: ppc-corenet: Fix Section mismatch warning"
	2. http://patchwork.ozlabs.org/patch/417295/
		powerpc: call of_clk_init() from time_init()
	3. http://patchwork.ozlabs.org/patch/417297/
		clk: ppc-corenet: fix section mismatch warning

 drivers/clk/clk-ppc-corenet.c | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c
index 57a2de4..5e9bb18 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-ppc-corenet.c
@@ -19,6 +19,7 @@
 struct cmux_clk {
 	struct clk_hw hw;
 	void __iomem *reg;
+	unsigned int clk_per_pll;
 	u32 flags;
 };
 
@@ -27,14 +28,12 @@ struct cmux_clk {
 #define CLKSEL_ADJUST		BIT(0)
 #define to_cmux_clk(p)		container_of(p, struct cmux_clk, hw)
 
-static unsigned int clocks_per_pll;
-
 static int cmux_set_parent(struct clk_hw *hw, u8 idx)
 {
 	struct cmux_clk *clk = to_cmux_clk(hw);
 	u32 clksel;
 
-	clksel = ((idx / clocks_per_pll) << 2) + idx % clocks_per_pll;
+	clksel = ((idx / clk->clk_per_pll) << 2) + idx % clk->clk_per_pll;
 	if (clk->flags & CLKSEL_ADJUST)
 		clksel += 8;
 	clksel = (clksel & 0xf) << CLKSEL_SHIFT;
@@ -52,7 +51,7 @@ static u8 cmux_get_parent(struct clk_hw *hw)
 	clksel = (clksel >> CLKSEL_SHIFT) & 0xf;
 	if (clk->flags & CLKSEL_ADJUST)
 		clksel -= 8;
-	clksel = (clksel >> 2) * clocks_per_pll + clksel % 4;
+	clksel = (clksel >> 2) * clk->clk_per_pll + clksel % 4;
 
 	return clksel;
 }
@@ -72,6 +71,7 @@ static void __init core_mux_init(struct device_node *np)
 	u32	offset;
 	const char *clk_name;
 	const char **parent_names;
+	struct of_phandle_args clkspec;
 
 	rc = of_property_read_u32(np, "reg", &offset);
 	if (rc) {
@@ -105,6 +105,17 @@ static void __init core_mux_init(struct device_node *np)
 		goto err_clk;
 	}
 
+	rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0,
+					&clkspec);
+	if (rc) {
+		pr_err("%s: parse clock node error\n", __func__);
+		goto err_clk;
+	}
+
+	cmux_clk->clk_per_pll = of_property_count_strings(clkspec.np,
+			"clock-output-names");
+	of_node_put(clkspec.np);
+
 	node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen");
 	if (node && (offset >= 0x80))
 		cmux_clk->flags = CLKSEL_ADJUST;
@@ -181,9 +192,6 @@ static void __init core_pll_init(struct device_node *np)
 		goto err_map;
 	}
 
-	/* output clock number per PLL */
-	clocks_per_pll = count;
-
 	subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL);
 	if (!subclks) {
 		pr_err("%s: could not allocate subclks\n", __func__);
-- 
2.1.0.27.g96db324

[PATCH 2/2] clk: ppc-corenet: rename driver to clk-qoriq

[Yuantian.Tang]

From: Tang Yuantian <Yuantian.Tang@freescale.com>

Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
 Documentation/devicetree/bindings/clock/qoriq-clock.txt |  5 +++--
 drivers/clk/Kconfig                                     | 10 +++++-----
 drivers/clk/Makefile                                    |  2 +-
 drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c}          |  6 +++---
 drivers/cpufreq/Kconfig.powerpc                         |  2 +-
 5 files changed, 13 insertions(+), 12 deletions(-)
 rename drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} (98%)

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 266ff9d..df4a259 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -1,6 +1,6 @@
-* Clock Block on Freescale CoreNet Platforms
+* Clock Block on Freescale QorIQ Platforms
 
-Freescale CoreNet chips take primary clocking input from the external
+Freescale qoriq chips take primary clocking input from the external
 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
 multiple phase locked loops (PLL) to create a variety of frequencies
 which can then be passed to a variety of internal logic, including
@@ -29,6 +29,7 @@ Required properties:
 	* "fsl,t4240-clockgen"
 	* "fsl,b4420-clockgen"
 	* "fsl,b4860-clockgen"
+	* "fsl,ls1021a-clockgen"
 	Chassis clock strings include:
 	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
 	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 3f44f29..a896fbc 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -101,12 +101,12 @@ config COMMON_CLK_AXI_CLKGEN
 	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
 	  FPGAs. It is commonly used in Analog Devices' reference designs.
 
-config CLK_PPC_CORENET
-	bool "Clock driver for PowerPC corenet platforms"
-	depends on PPC_E500MC && OF
+config CLK_QORIQ
+	bool "Clock driver for Freescale QorIQ platforms"
+	depends on (PPC_E500MC || ARM) && OF
 	---help---
-	  This adds the clock driver support for Freescale PowerPC corenet
-	  platforms using common clock framework.
+	  This adds the clock driver support for Freescale QorIQ platforms
+	  using common clock framework.
 
 config COMMON_CLK_XGENE
 	bool "Clock driver for APM XGene SoC"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d5fba5b..4ff94cd 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,7 +30,7 @@ obj-$(CONFIG_ARCH_MOXART)		+= clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK)		+= clk-nomadik.o
 obj-$(CONFIG_ARCH_NSPIRE)		+= clk-nspire.o
 obj-$(CONFIG_COMMON_CLK_PALMAS)		+= clk-palmas.o
-obj-$(CONFIG_CLK_PPC_CORENET)		+= clk-ppc-corenet.o
+obj-$(CONFIG_CLK_QORIQ)			+= clk-qoriq.o
 obj-$(CONFIG_COMMON_CLK_RK808)		+= clk-rk808.o
 obj-$(CONFIG_COMMON_CLK_S2MPS11)	+= clk-s2mps11.o
 obj-$(CONFIG_COMMON_CLK_SI5351)		+= clk-si5351.o
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c
similarity index 98%
rename from drivers/clk/clk-ppc-corenet.c
rename to drivers/clk/clk-qoriq.c
index 5e9bb18..f9b7eb4 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-qoriq.c
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- * clock driver for Freescale PowerPC corenet SoCs.
+ * clock driver for Freescale QorIQ SoCs.
  */
 #include <linux/clk-provider.h>
 #include <linux/io.h>
@@ -166,7 +166,7 @@ static void __init core_pll_init(struct device_node *np)
 
 	base = of_iomap(np, 0);
 	if (!base) {
-		pr_err("clk-ppc: iomap error\n");
+		pr_err("clk-qoriq: iomap error\n");
 		return;
 	}
 
@@ -260,7 +260,7 @@ static void __init sysclk_init(struct device_node *node)
 	u32 rate;
 
 	if (!np) {
-		pr_err("ppc-clk: could not get parent node\n");
+		pr_err("qoriq-clk: could not get parent node\n");
 		return;
 	}
 
diff --git a/drivers/cpufreq/Kconfig.powerpc b/drivers/cpufreq/Kconfig.powerpc
index 72564b7..7ea2441 100644
--- a/drivers/cpufreq/Kconfig.powerpc
+++ b/drivers/cpufreq/Kconfig.powerpc
@@ -26,7 +26,7 @@ config CPU_FREQ_MAPLE
 config PPC_CORENET_CPUFREQ
 	tristate "CPU frequency scaling driver for Freescale E500MC SoCs"
 	depends on PPC_E500MC && OF && COMMON_CLK
-	select CLK_PPC_CORENET
+	select CLK_QORIQ
 	help
 	  This adds the CPUFreq driver support for Freescale e500mc,
 	  e5500 and e6500 series SoCs which are capable of changing
-- 
2.1.0.27.g96db324

Re: [PATCH 1/2] clock: redefine variable clocks_per_pll as a struct member

[Mike Turquette]

Quoting Yuantian.Tang@freescale.com (2015-01-14 22:03:40)
> From: Tang Yuantian <Yuantian.Tang@freescale.com>
> =

> redefine variable clocks_per_pll as a struct member
> =

> If there are multiple PLL clock nodes, this variable will
> get overwritten. Redefining it as a struct member can avoid that.
> =

> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>

Applied to clk-next towards 3.20.

Regards,
Mike

> ---
> These patches are based on following three patches which are acked
> by Scott wood <scottwood@freescale.com>:
>         1. http://patchwork.ozlabs.org/patch/417292/
>                 Revert "clk: ppc-corenet: Fix Section mismatch warning"
>         2. http://patchwork.ozlabs.org/patch/417295/
>                 powerpc: call of_clk_init() from time_init()
>         3. http://patchwork.ozlabs.org/patch/417297/
>                 clk: ppc-corenet: fix section mismatch warning
> =

>  drivers/clk/clk-ppc-corenet.c | 22 +++++++++++++++-------
>  1 file changed, 15 insertions(+), 7 deletions(-)
> =

> diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c
> index 57a2de4..5e9bb18 100644
> --- a/drivers/clk/clk-ppc-corenet.c
> +++ b/drivers/clk/clk-ppc-corenet.c
> @@ -19,6 +19,7 @@
>  struct cmux_clk {
>         struct clk_hw hw;
>         void __iomem *reg;
> +       unsigned int clk_per_pll;
>         u32 flags;
>  };
>  =

> @@ -27,14 +28,12 @@ struct cmux_clk {
>  #define CLKSEL_ADJUST          BIT(0)
>  #define to_cmux_clk(p)         container_of(p, struct cmux_clk, hw)
>  =

> -static unsigned int clocks_per_pll;
> -
>  static int cmux_set_parent(struct clk_hw *hw, u8 idx)
>  {
>         struct cmux_clk *clk =3D to_cmux_clk(hw);
>         u32 clksel;
>  =

> -       clksel =3D ((idx / clocks_per_pll) << 2) + idx % clocks_per_pll;
> +       clksel =3D ((idx / clk->clk_per_pll) << 2) + idx % clk->clk_per_p=
ll;
>         if (clk->flags & CLKSEL_ADJUST)
>                 clksel +=3D 8;
>         clksel =3D (clksel & 0xf) << CLKSEL_SHIFT;
> @@ -52,7 +51,7 @@ static u8 cmux_get_parent(struct clk_hw *hw)
>         clksel =3D (clksel >> CLKSEL_SHIFT) & 0xf;
>         if (clk->flags & CLKSEL_ADJUST)
>                 clksel -=3D 8;
> -       clksel =3D (clksel >> 2) * clocks_per_pll + clksel % 4;
> +       clksel =3D (clksel >> 2) * clk->clk_per_pll + clksel % 4;
>  =

>         return clksel;
>  }
> @@ -72,6 +71,7 @@ static void __init core_mux_init(struct device_node *np)
>         u32     offset;
>         const char *clk_name;
>         const char **parent_names;
> +       struct of_phandle_args clkspec;
>  =

>         rc =3D of_property_read_u32(np, "reg", &offset);
>         if (rc) {
> @@ -105,6 +105,17 @@ static void __init core_mux_init(struct device_node =
*np)
>                 goto err_clk;
>         }
>  =

> +       rc =3D of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0,
> +                                       &clkspec);
> +       if (rc) {
> +               pr_err("%s: parse clock node error\n", __func__);
> +               goto err_clk;
> +       }
> +
> +       cmux_clk->clk_per_pll =3D of_property_count_strings(clkspec.np,
> +                       "clock-output-names");
> +       of_node_put(clkspec.np);
> +
>         node =3D of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen"=
);
>         if (node && (offset >=3D 0x80))
>                 cmux_clk->flags =3D CLKSEL_ADJUST;
> @@ -181,9 +192,6 @@ static void __init core_pll_init(struct device_node *=
np)
>                 goto err_map;
>         }
>  =

> -       /* output clock number per PLL */
> -       clocks_per_pll =3D count;
> -
>         subclks =3D kzalloc(sizeof(struct clk *) * count, GFP_KERNEL);
>         if (!subclks) {
>                 pr_err("%s: could not allocate subclks\n", __func__);
> -- =

> 2.1.0.27.g96db324
>=20