Re: [PATCH v3 2/2] x86: Add support for the clwb instruction

[Borislav Petkov <bp@alien8.de>]

On Tue, Jan 27, 2015 at 09:53:51AM -0700, Ross Zwisler wrote:
> Add support for the new clwb (cache line write back) instruction.  This
> instruction was announced in the document "Intel Architecture
> Instruction Set Extensions Programming Reference" with reference number
> 319433-022.

...

> After this function completes the data pointed to by vaddr is has been
> accepted to memory and will be durable if the vaddr points to
> persistent memory.
> 
> Regarding the details of how the alternatives assembly is set up, we
> need one additional byte at the beginning of the clflush so that we can
> flip it into a clflushopt by changing that byte into a 0x66 prefix.  Two
> options are to either insert a 1 byte ASM_NOP1, or to add a 1 byte
> NOP_DS_PREFIX.  Both have no functional effect with the plain clflush,
> but I've been told that executing a clflush + prefix should be faster
> than executing a clflush + NOP.
> 
> We had to hard code the assembly for clwb because, lacking the ability
> to assemble the clwb instruction itself, the next closest thing is to
> have an xsaveopt instruction with a 0x66 prefix.  Unfortunately xsaveopt
> itself is also relatively new, and isn't included by all the GCC
> versions that the kernel needs to support.
> 
> Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com>
> Cc: H Peter Anvin <h.peter.anvin@intel.com>
> Cc: Ingo Molnar <mingo@kernel.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Borislav Petkov <bp@alien8.de>

Acked-by: Borislav Petkov <bp@suse.de>

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--