From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/skl: Enable eDRAM for gen9 as well
Date: Fri, 30 Jan 2015 19:10:37 +0200 [thread overview]
Message-ID: <20150130171037.GC19354@intel.com> (raw)
In-Reply-To: <1422535355-4574-1-git-send-email-damien.lespiau@intel.com>
On Thu, Jan 29, 2015 at 12:42:35PM +0000, Damien Lespiau wrote:
> Suggested-by: Daniel Vetter <daniel@ffwll.ch>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 0e9bf82..0a1089b 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -329,7 +329,8 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
> if (HAS_FPGA_DBG_UNCLAIMED(dev))
> __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
>
> - if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
> + if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
> + INTEL_INFO(dev)->gen >= 9) &&
Should this perhaps be IS_SKYLAKE()?
> (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
> /* The docs do not explain exactly how the calculation can be
> * made. It is somewhat guessable, but for now, it's always
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2015-01-30 17:10 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-29 12:42 [PATCH] drm/i915/skl: Enable eDRAM for gen9 as well Damien Lespiau
2015-01-30 16:23 ` Daniel Vetter
2015-02-02 15:08 ` Damien Lespiau
2015-01-30 17:10 ` Ville Syrjälä [this message]
2015-01-31 17:30 ` shuang.he
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