From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Brian Norris <computersforpeace@gmail.com>
Cc: Lior Amsalem <alior@marvell.com>, Andrew Lunn <andrew@lunn.ch>,
Jason Cooper <jason@lakedaemon.net>,
Tawfik Bayouk <tawfik@marvell.com>,
Thomas Petazzoni <thomas@free-electrons.com>,
Seif Mazareeb <seif@marvell.com>,
linux-kernel@vger.kernel.org, stable@vger.kernel.org,
Sudhakar Gundubogula <sudhakar@marvell.com>,
Nadav Haklai <nadavh@marvell.com>,
Boris Brezillon <boris@free-electrons.com>,
linux-mtd@lists.infradead.org,
Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
Gregory Clement <gregory.clement@free-electrons.com>,
linux-arm-kernel@lists.infradead.org,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
Date: Wed, 4 Feb 2015 10:13:17 +0100 [thread overview]
Message-ID: <20150204091317.GA5492@lukather> (raw)
In-Reply-To: <1422284164-16867-2-git-send-email-maxime.ripard@free-electrons.com>
[-- Attachment #1: Type: text/plain, Size: 857 bytes --]
Hi Brian,
On Mon, Jan 26, 2015 at 03:56:03PM +0100, Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
>
> However, during a read PIO access, the datasheet specifies that after each 32
> bits read in that register, when BCH is enabled, we have to make sure that the
> RDDREQ bit is set in the NDSR register.
>
> This fixes an issue that was seen on the Armada 385, and presumably other mvebu
> SoCs, when a read on a newly erased page would end up in the driver reporting a
> timeout from the NAND.
>
> Cc: <stable@vger.kernel.org> # v3.14
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Any chance for this fix to come in 3.19?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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WARNING: multiple messages have this Message-ID (diff)
From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
Date: Wed, 4 Feb 2015 10:13:17 +0100 [thread overview]
Message-ID: <20150204091317.GA5492@lukather> (raw)
In-Reply-To: <1422284164-16867-2-git-send-email-maxime.ripard@free-electrons.com>
Hi Brian,
On Mon, Jan 26, 2015 at 03:56:03PM +0100, Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
>
> However, during a read PIO access, the datasheet specifies that after each 32
> bits read in that register, when BCH is enabled, we have to make sure that the
> RDDREQ bit is set in the NDSR register.
>
> This fixes an issue that was seen on the Armada 385, and presumably other mvebu
> SoCs, when a read on a newly erased page would end up in the driver reporting a
> timeout from the NAND.
>
> Cc: <stable@vger.kernel.org> # v3.14
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Any chance for this fix to come in 3.19?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Brian Norris <computersforpeace@gmail.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>,
Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
linux-mtd@lists.infradead.org,
Boris Brezillon <boris@free-electrons.com>,
Thomas Petazzoni <thomas@free-electrons.com>,
linux-arm-kernel@lists.infradead.org,
Tawfik Bayouk <tawfik@marvell.com>,
Nadav Haklai <nadavh@marvell.com>,
Lior Amsalem <alior@marvell.com>,
linux-kernel@vger.kernel.org,
Sudhakar Gundubogula <sudhakar@marvell.com>,
Seif Mazareeb <seif@marvell.com>,
stable@vger.kernel.org
Subject: Re: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
Date: Wed, 4 Feb 2015 10:13:17 +0100 [thread overview]
Message-ID: <20150204091317.GA5492@lukather> (raw)
In-Reply-To: <1422284164-16867-2-git-send-email-maxime.ripard@free-electrons.com>
[-- Attachment #1: Type: text/plain, Size: 857 bytes --]
Hi Brian,
On Mon, Jan 26, 2015 at 03:56:03PM +0100, Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
>
> However, during a read PIO access, the datasheet specifies that after each 32
> bits read in that register, when BCH is enabled, we have to make sure that the
> RDDREQ bit is set in the NDSR register.
>
> This fixes an issue that was seen on the Armada 385, and presumably other mvebu
> SoCs, when a read on a newly erased page would end up in the driver reporting a
> timeout from the NAND.
>
> Cc: <stable@vger.kernel.org> # v3.14
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Any chance for this fix to come in 3.19?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2015-02-04 9:13 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-26 14:56 [PATCH v2 0/2] ARM: mvebu: a385-db-ap: Enable the NAND controller Maxime Ripard
2015-01-26 14:56 ` Maxime Ripard
2015-01-26 14:56 ` Maxime Ripard
2015-01-26 14:56 ` [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining Maxime Ripard
2015-01-26 14:56 ` Maxime Ripard
2015-01-26 14:56 ` Maxime Ripard
2015-02-04 9:13 ` Maxime Ripard [this message]
2015-02-04 9:13 ` Maxime Ripard
2015-02-04 9:13 ` Maxime Ripard
2015-02-04 10:10 ` Boris Brezillon
2015-02-04 10:10 ` Boris Brezillon
2015-02-04 10:10 ` Boris Brezillon
2015-02-06 1:08 ` Brian Norris
2015-02-06 1:08 ` Brian Norris
2015-02-06 1:08 ` Brian Norris
2015-02-06 8:13 ` Boris Brezillon
2015-02-06 8:13 ` Boris Brezillon
2015-02-06 8:13 ` Boris Brezillon
2015-02-06 8:33 ` Brian Norris
2015-02-06 8:33 ` Brian Norris
2015-02-06 8:33 ` Brian Norris
2015-02-06 14:17 ` Ezequiel Garcia
2015-02-06 14:17 ` Ezequiel Garcia
2015-02-06 14:17 ` Ezequiel Garcia
2015-02-06 14:17 ` Ezequiel Garcia
2015-02-06 19:38 ` Brian Norris
2015-02-06 19:38 ` Brian Norris
2015-02-06 19:38 ` Brian Norris
2015-02-06 20:33 ` Maxime Ripard
2015-02-06 20:33 ` Maxime Ripard
2015-02-06 20:33 ` Maxime Ripard
2015-01-26 14:56 ` [PATCH v2 2/2] ARM: mvebu: a385-db-ap: Enable the NAND Maxime Ripard
2015-01-26 14:56 ` Maxime Ripard
2015-01-26 14:56 ` Maxime Ripard
2015-01-28 2:06 ` Ezequiel Garcia
2015-01-28 2:06 ` Ezequiel Garcia
2015-01-28 2:06 ` Ezequiel Garcia
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