From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Lior Amsalem <alior@marvell.com>, Andrew Lunn <andrew@lunn.ch>,
Jason Cooper <jason@lakedaemon.net>,
Tawfik Bayouk <tawfik@marvell.com>,
Thomas Petazzoni <thomas@free-electrons.com>,
Seif Mazareeb <seif@marvell.com>,
linux-kernel@vger.kernel.org, stable@vger.kernel.org,
Sudhakar Gundubogula <sudhakar@marvell.com>,
Nadav Haklai <nadavh@marvell.com>,
Boris Brezillon <boris@free-electrons.com>,
linux-mtd@lists.infradead.org,
Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
Gregory Clement <gregory.clement@free-electrons.com>,
Brian Norris <computersforpeace@gmail.com>,
linux-arm-kernel@lists.infradead.org,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
Date: Mon, 16 Feb 2015 21:58:25 +0100 [thread overview]
Message-ID: <20150216205825.GG25269@lukather> (raw)
In-Reply-To: <87oaotaa6r.fsf@free.fr>
[-- Attachment #1: Type: text/plain, Size: 2358 bytes --]
Hi Robert,
On Mon, Feb 16, 2015 at 09:11:24PM +0100, Robert Jarzmik wrote:
> Maxime Ripard <maxime.ripard@free-electrons.com> writes:
>
> > drivers/mtd/nand/pxa3xx_nand.c | 47 ++++++++++++++++++++++++++++++++++++------
> > 1 file changed, 41 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> > index 96b0b1d27df1..b2d8d6960765 100644
> > --- a/drivers/mtd/nand/pxa3xx_nand.c
> > +++ b/drivers/mtd/nand/pxa3xx_nand.c
> > @@ -480,6 +480,41 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
> > nand_writel(info, NDCR, ndcr | int_mask);
> > }
> >
> > +static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
> > +{
> > + if (info->ecc_bch) {
> > + int index = 0;
> > +
> > + while (index < (len * 4)) {
> > + u32 timeout;
> > +
> > + __raw_readsl(info->mmio_base + NDDB, data + index, 8);
> > +
> > + /*
> > + * According to the datasheet, when reading
> > + * from NDDB with BCH enabled, after each 32
> > + * bytes reads, we have to make sure that the
> > + * NDSR.RDDREQ bit is set
> > + */
> > + for (timeout = 0;
> > + !(nand_readl(info, NDSR) & NDSR_RDDREQ);
> > + timeout++) {
> > + if (timeout >= 5) {
> > + dev_err(&info->pdev->dev,
> > + "Timeout on RDDREQ while draining the FIFO\n");
> > + return;
> > + }
> > +
> > + mdelay(1);
> So in worst case, we'll end up with 4 times mdelay(1) times len / 32.
> For a 2048 page, it is : 256ms where everything is stuck (mdelay and not
> msleep).
>
> I know you had no choice because this is called from interrupt handler (top
> half). But having a irq handler and a irq thread handler would solve that issue,
> and you'll end up with msleep(1) in this code.
>
> I don't think an mdelay(256) is acceptable.
That's very true that this driver would need some love, but
valentine's day was last week.
I'm sorry, but this is a patch targeted for stable. This is a pure
bugfix. I won't rewrite the whole driver solely to make the driver
better, especially since that would make such a patch (or more likely
a whole serie) unsuitable for stable.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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WARNING: multiple messages have this Message-ID (diff)
From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
Date: Mon, 16 Feb 2015 21:58:25 +0100 [thread overview]
Message-ID: <20150216205825.GG25269@lukather> (raw)
In-Reply-To: <87oaotaa6r.fsf@free.fr>
Hi Robert,
On Mon, Feb 16, 2015 at 09:11:24PM +0100, Robert Jarzmik wrote:
> Maxime Ripard <maxime.ripard@free-electrons.com> writes:
>
> > drivers/mtd/nand/pxa3xx_nand.c | 47 ++++++++++++++++++++++++++++++++++++------
> > 1 file changed, 41 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> > index 96b0b1d27df1..b2d8d6960765 100644
> > --- a/drivers/mtd/nand/pxa3xx_nand.c
> > +++ b/drivers/mtd/nand/pxa3xx_nand.c
> > @@ -480,6 +480,41 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
> > nand_writel(info, NDCR, ndcr | int_mask);
> > }
> >
> > +static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
> > +{
> > + if (info->ecc_bch) {
> > + int index = 0;
> > +
> > + while (index < (len * 4)) {
> > + u32 timeout;
> > +
> > + __raw_readsl(info->mmio_base + NDDB, data + index, 8);
> > +
> > + /*
> > + * According to the datasheet, when reading
> > + * from NDDB with BCH enabled, after each 32
> > + * bytes reads, we have to make sure that the
> > + * NDSR.RDDREQ bit is set
> > + */
> > + for (timeout = 0;
> > + !(nand_readl(info, NDSR) & NDSR_RDDREQ);
> > + timeout++) {
> > + if (timeout >= 5) {
> > + dev_err(&info->pdev->dev,
> > + "Timeout on RDDREQ while draining the FIFO\n");
> > + return;
> > + }
> > +
> > + mdelay(1);
> So in worst case, we'll end up with 4 times mdelay(1) times len / 32.
> For a 2048 page, it is : 256ms where everything is stuck (mdelay and not
> msleep).
>
> I know you had no choice because this is called from interrupt handler (top
> half). But having a irq handler and a irq thread handler would solve that issue,
> and you'll end up with msleep(1) in this code.
>
> I don't think an mdelay(256) is acceptable.
That's very true that this driver would need some love, but
valentine's day was last week.
I'm sorry, but this is a patch targeted for stable. This is a pure
bugfix. I won't rewrite the whole driver solely to make the driver
better, especially since that would make such a patch (or more likely
a whole serie) unsuitable for stable.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Gregory Clement <gregory.clement@free-electrons.com>,
Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
Brian Norris <computersforpeace@gmail.com>,
Lior Amsalem <alior@marvell.com>,
Tawfik Bayouk <tawfik@marvell.com>,
Thomas Petazzoni <thomas@free-electrons.com>,
Seif Mazareeb <seif@marvell.com>,
linux-kernel@vger.kernel.org, stable@vger.kernel.org,
Sudhakar Gundubogula <sudhakar@marvell.com>,
Nadav Haklai <nadavh@marvell.com>,
Boris Brezillon <boris@free-electrons.com>,
linux-mtd@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
Date: Mon, 16 Feb 2015 21:58:25 +0100 [thread overview]
Message-ID: <20150216205825.GG25269@lukather> (raw)
In-Reply-To: <87oaotaa6r.fsf@free.fr>
[-- Attachment #1: Type: text/plain, Size: 2358 bytes --]
Hi Robert,
On Mon, Feb 16, 2015 at 09:11:24PM +0100, Robert Jarzmik wrote:
> Maxime Ripard <maxime.ripard@free-electrons.com> writes:
>
> > drivers/mtd/nand/pxa3xx_nand.c | 47 ++++++++++++++++++++++++++++++++++++------
> > 1 file changed, 41 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> > index 96b0b1d27df1..b2d8d6960765 100644
> > --- a/drivers/mtd/nand/pxa3xx_nand.c
> > +++ b/drivers/mtd/nand/pxa3xx_nand.c
> > @@ -480,6 +480,41 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
> > nand_writel(info, NDCR, ndcr | int_mask);
> > }
> >
> > +static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
> > +{
> > + if (info->ecc_bch) {
> > + int index = 0;
> > +
> > + while (index < (len * 4)) {
> > + u32 timeout;
> > +
> > + __raw_readsl(info->mmio_base + NDDB, data + index, 8);
> > +
> > + /*
> > + * According to the datasheet, when reading
> > + * from NDDB with BCH enabled, after each 32
> > + * bytes reads, we have to make sure that the
> > + * NDSR.RDDREQ bit is set
> > + */
> > + for (timeout = 0;
> > + !(nand_readl(info, NDSR) & NDSR_RDDREQ);
> > + timeout++) {
> > + if (timeout >= 5) {
> > + dev_err(&info->pdev->dev,
> > + "Timeout on RDDREQ while draining the FIFO\n");
> > + return;
> > + }
> > +
> > + mdelay(1);
> So in worst case, we'll end up with 4 times mdelay(1) times len / 32.
> For a 2048 page, it is : 256ms where everything is stuck (mdelay and not
> msleep).
>
> I know you had no choice because this is called from interrupt handler (top
> half). But having a irq handler and a irq thread handler would solve that issue,
> and you'll end up with msleep(1) in this code.
>
> I don't think an mdelay(256) is acceptable.
That's very true that this driver would need some love, but
valentine's day was last week.
I'm sorry, but this is a patch targeted for stable. This is a pure
bugfix. I won't rewrite the whole driver solely to make the driver
better, especially since that would make such a patch (or more likely
a whole serie) unsuitable for stable.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
next prev parent reply other threads:[~2015-02-16 20:58 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-16 12:51 [PATCH v3 0/2] ARM: mvebu: a385-db-ap: Enable the NAND controller Maxime Ripard
2015-02-16 12:51 ` Maxime Ripard
2015-02-16 12:51 ` Maxime Ripard
2015-02-16 12:51 ` [PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining Maxime Ripard
2015-02-16 12:51 ` Maxime Ripard
2015-02-16 12:51 ` Maxime Ripard
2015-02-16 13:34 ` Boris Brezillon
2015-02-16 13:34 ` Boris Brezillon
2015-02-16 13:34 ` Boris Brezillon
2015-02-16 13:35 ` Ezequiel Garcia
2015-02-16 13:35 ` Ezequiel Garcia
2015-02-16 13:35 ` Ezequiel Garcia
2015-02-16 13:35 ` Ezequiel Garcia
2015-02-16 16:49 ` Maxime Ripard
2015-02-16 16:49 ` Maxime Ripard
2015-02-16 16:49 ` Maxime Ripard
2015-02-16 16:27 ` Thomas Petazzoni
2015-02-16 16:27 ` Thomas Petazzoni
2015-02-16 16:27 ` Thomas Petazzoni
2015-02-16 16:41 ` Maxime Ripard
2015-02-16 16:41 ` Maxime Ripard
2015-02-16 16:41 ` Maxime Ripard
2015-02-16 16:57 ` Ezequiel Garcia
2015-02-16 16:57 ` Ezequiel Garcia
2015-02-16 16:57 ` Ezequiel Garcia
2015-02-16 16:57 ` Ezequiel Garcia
2015-02-17 10:29 ` Maxime Ripard
2015-02-17 10:29 ` Maxime Ripard
2015-02-17 10:29 ` Maxime Ripard
2015-02-16 20:11 ` Robert Jarzmik
2015-02-16 20:11 ` Robert Jarzmik
2015-02-16 20:11 ` Robert Jarzmik
2015-02-16 20:58 ` Maxime Ripard [this message]
2015-02-16 20:58 ` Maxime Ripard
2015-02-16 20:58 ` Maxime Ripard
2015-02-16 21:36 ` Robert Jarzmik
2015-02-16 21:36 ` Robert Jarzmik
2015-02-16 21:36 ` Robert Jarzmik
2015-02-17 9:47 ` Maxime Ripard
2015-02-17 9:47 ` Maxime Ripard
2015-02-17 9:47 ` Maxime Ripard
2015-02-17 10:37 ` Maxime Ripard
2015-02-17 10:37 ` Maxime Ripard
2015-02-17 10:37 ` Maxime Ripard
2015-02-17 17:07 ` Robert Jarzmik
2015-02-17 17:07 ` Robert Jarzmik
2015-02-17 17:07 ` Robert Jarzmik
2015-02-17 17:16 ` Ezequiel Garcia
2015-02-17 17:16 ` Ezequiel Garcia
2015-02-17 17:16 ` Ezequiel Garcia
2015-02-17 17:16 ` Ezequiel Garcia
2015-02-24 3:45 ` Brian Norris
2015-02-24 3:45 ` Brian Norris
2015-02-24 3:45 ` Brian Norris
2015-02-24 8:17 ` Maxime Ripard
2015-02-24 8:17 ` Maxime Ripard
2015-02-24 8:17 ` Maxime Ripard
2015-02-16 12:51 ` [PATCH v3 2/2] ARM: mvebu: a385-db-ap: Enable the NAND Maxime Ripard
2015-02-16 12:51 ` Maxime Ripard
2015-02-16 12:51 ` Maxime Ripard
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