From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 09/12] drm/i915: Rewrite VLV/CHV watermark code
Date: Thu, 5 Mar 2015 19:22:19 +0200 [thread overview]
Message-ID: <20150305172219.GI11371@intel.com> (raw)
In-Reply-To: <1423574909-1074-10-git-send-email-ville.syrjala@linux.intel.com>
On Tue, Feb 10, 2015 at 03:28:26PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Assuming the PND deadline mechanism works reasonably we should do
> memory requests as early as possible so that PND has schedule the
> requests more intelligently. Currently we're still calculating
> the watermarks as if VLV/CHV are identical to g4x, which isn't
> the case.
>
> The current code also seems to calculate insufficient watermarks
> and hence we're seeing some underruns, especially on high resolution
> displays.
>
> To fix it just rip out the current code and replace is with something
> that tries to utilize PND as efficiently as possible.
>
> We now calculate the WM watermark to trigger when the FIFO still has
> 256us worth of data. 256us is the maximum deadline value supoorted by
> PND, so issuing memory requests earlier would mean we probably couldn't
> utilize the full FIFO as PND would attempt to return the data at
> least in at least 256us. We also clamp the watermark to at least 8
> cachelines as that's the magic watermark that enabling trickle feed
> would also impose. I'm assuming it matches some burst size.
>
> In theory we could just enable trickle feed and ignore the WM values,
> except trickle feed doesn't work with max fifo mode anyway, so we'd
> still need to calculate the SR watermarks. It seems cleaner to just
> disable trickle feed and calculate all watermarks the same way. Also
> trickle feed wouldn't account for the 256us max deadline value, thoguh
> that may be a moot point in non-max fifo mode sicne the FIFOs are fairly
> small.
>
> On VLV max fifo mode can be used with either primary or sprite planes.
> So the code now also checks all the planes (apart from the cursor)
> when calculating the SR plane watermark.
>
> We don't have to worry about the WM1 watermarks since we're using the
> PND deadline scheme which means the hardware ignores WM1 values.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
This patch still lacks review. Any takers?
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2015-03-05 17:22 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-10 13:28 [PATCH 00/12] drm/i915: Redo VLV/CHV watermark code ville.syrjala
2015-02-10 13:28 ` [PATCH 01/12] drm/i915: Reduce CHV DDL multiplier to 16/8 ville.syrjala
2015-02-27 17:36 ` Jesse Barnes
2015-02-27 18:02 ` Ville Syrjälä
[not found] ` <54F42A58.1020103@linux.intel.com>
2015-03-02 9:36 ` Arun R Murthy
2015-02-10 13:28 ` [PATCH 02/12] drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines ville.syrjala
2015-02-27 17:38 ` Jesse Barnes
2015-02-27 18:06 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 03/12] drm/i915: Simplify VLV drain latency computation ville.syrjala
2015-02-27 17:40 ` Jesse Barnes
2015-02-10 13:28 ` [PATCH 04/12] drm/i915: Hide VLV DDL precision handling ville.syrjala
2015-02-27 17:46 ` Jesse Barnes
2015-02-10 13:28 ` [PATCH 05/12] drm/i915: Reorganize VLV DDL setup ville.syrjala
2015-02-27 17:52 ` Jesse Barnes
2015-02-10 13:28 ` [PATCH 06/12] drm/i915: Pass plane to vlv_compute_drain_latency() ville.syrjala
2015-02-27 17:57 ` Jesse Barnes
2015-02-27 18:09 ` Ville Syrjälä
2015-02-27 20:37 ` Jesse Barnes
2015-03-02 14:44 ` Daniel Vetter
2015-03-02 14:49 ` Ville Syrjälä
2015-03-02 17:18 ` Daniel Vetter
2015-02-10 13:28 ` [PATCH 07/12] drm/i915: Read out display FIFO size on VLV/CHV ville.syrjala
2015-02-12 18:59 ` [PATCH v2 " ville.syrjala
2015-02-27 18:04 ` Jesse Barnes
2015-02-10 13:28 ` [PATCH 08/12] drm/i915: Make sure PND deadline mode is enabled " ville.syrjala
2015-02-27 20:38 ` Jesse Barnes
2015-02-27 20:48 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 09/12] drm/i915: Rewrite VLV/CHV watermark code ville.syrjala
2015-03-05 17:22 ` Ville Syrjälä [this message]
2015-02-10 13:28 ` [PATCH 10/12] drm/i915: Support maxfifo with two planes on CHV ville.syrjala
2015-03-04 14:04 ` Purushothaman, Vijay A
2015-03-04 14:50 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 11/12] drm/i915: Program PFI credits for VLV ville.syrjala
2015-03-04 14:25 ` Purushothaman, Vijay A
2015-03-04 15:06 ` Ville Syrjälä
2015-03-04 15:26 ` Ville Syrjälä
2015-02-10 13:28 ` [PATCH 12/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV ville.syrjala
2015-02-11 0:01 ` shuang.he
2015-02-26 19:01 ` [PATCH v2 " ville.syrjala
2015-03-04 14:28 ` [PATCH " Purushothaman, Vijay A
2015-03-04 15:07 ` Ville Syrjälä
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