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From: Wolfram Sang <wsa@the-dreams.de>
To: Simon Horman <horms@verge.net.au>
Cc: Yoshihiro Kaneko <ykaneko0929@gmail.com>,
	linux-i2c@vger.kernel.org, Magnus Damm <magnus.damm@gmail.com>,
	linux-sh@vger.kernel.org
Subject: Re: [PATCH/RFC] i2c: rcar: Fix order of restart and clear status
Date: Fri, 6 Mar 2015 23:05:31 +0100	[thread overview]
Message-ID: <20150306220531.GA6572@katana> (raw)
In-Reply-To: <20150304040819.GB12776@verge.net.au>

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> I asked Kataoka-san about this and his response was as follows:

Thanks, Simon!

> If system(CPU) is busy, the driver can't clear the status register soon
> after kicking start.
> 
> If sequence of first start is as follows, there is a problem.
> Because H/W starts by 1.
> But sequence of re-start is as follows, there is no problem.
> Because H/W starts by 2.
> 
>   1. Issue START condition by ESG bit of ICMCR register.
>                   <--- If there is too much time, H/W finish transmitting
>                        and set status in status register.
>   2. Clear interrupt status (ICMSR).
>   3. Open interrupt mask.
>   4. Wait interrupt.
>                   <--- If status is cleared, interrupt does not occur.

I understand. I'll add this explanation to the patch and apply it soon.


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WARNING: multiple messages have this Message-ID (diff)
From: Wolfram Sang <wsa@the-dreams.de>
To: Simon Horman <horms@verge.net.au>
Cc: Yoshihiro Kaneko <ykaneko0929@gmail.com>,
	linux-i2c@vger.kernel.org, Magnus Damm <magnus.damm@gmail.com>,
	linux-sh@vger.kernel.org
Subject: Re: [PATCH/RFC] i2c: rcar: Fix order of restart and clear status
Date: Fri, 06 Mar 2015 22:05:31 +0000	[thread overview]
Message-ID: <20150306220531.GA6572@katana> (raw)
In-Reply-To: <20150304040819.GB12776@verge.net.au>

[-- Attachment #1: Type: text/plain, Size: 823 bytes --]


> I asked Kataoka-san about this and his response was as follows:

Thanks, Simon!

> If system(CPU) is busy, the driver can't clear the status register soon
> after kicking start.
> 
> If sequence of first start is as follows, there is a problem.
> Because H/W starts by 1.
> But sequence of re-start is as follows, there is no problem.
> Because H/W starts by 2.
> 
>   1. Issue START condition by ESG bit of ICMCR register.
>                   <--- If there is too much time, H/W finish transmitting
>                        and set status in status register.
>   2. Clear interrupt status (ICMSR).
>   3. Open interrupt mask.
>   4. Wait interrupt.
>                   <--- If status is cleared, interrupt does not occur.

I understand. I'll add this explanation to the patch and apply it soon.


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  reply	other threads:[~2015-03-06 22:05 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-15 14:43 [PATCH/RFC] i2c: rcar: Fix order of restart and clear status Yoshihiro Kaneko
2015-02-15 14:43 ` Yoshihiro Kaneko
2015-02-23 13:07 ` Wolfram Sang
2015-02-23 13:07   ` Wolfram Sang
2015-03-04  4:08   ` Simon Horman
2015-03-04  4:08     ` Simon Horman
2015-03-06 22:05     ` Wolfram Sang [this message]
2015-03-06 22:05       ` Wolfram Sang
2015-03-07 10:33       ` Wolfram Sang
2015-03-07 10:33         ` Wolfram Sang
2015-03-27 13:10         ` Wolfram Sang
2015-03-27 13:10           ` Wolfram Sang
2015-03-30  0:15           ` Simon Horman
2015-03-30  0:15             ` Simon Horman
2015-05-18  6:04             ` Simon Horman
2015-05-18  6:04               ` Simon Horman

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