* [PATCH] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
@ 2015-03-17 19:19 ` Peter Maydell
0 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2015-03-17 19:19 UTC (permalink / raw)
To: qemu-devel; +Cc: Greg Bellows, kvmarm, patches
The AArch64 SPSR_EL1 register is architecturally mandated to
be mapped to the AArch32 SPSR_svc register. This means its
state should live in QEMU's env->banked_spsr[1] field.
Correct the buggy regdef that put it in banked_spsr[0] instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 10886c5..d77c6de 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2438,7 +2438,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_ALIAS,
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
/* We rely on the access checks not allowing the guest to write to the
* state field when SPSel indicates that it's being used as the stack
* pointer.
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [Qemu-devel] [PATCH] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
@ 2015-03-17 19:19 ` Peter Maydell
0 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2015-03-17 19:19 UTC (permalink / raw)
To: qemu-devel
Cc: Greg Bellows, Alex Bennée, kvmarm, Christoffer Dall, patches
The AArch64 SPSR_EL1 register is architecturally mandated to
be mapped to the AArch32 SPSR_svc register. This means its
state should live in QEMU's env->banked_spsr[1] field.
Correct the buggy regdef that put it in banked_spsr[0] instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 10886c5..d77c6de 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2438,7 +2438,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_ALIAS,
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
/* We rely on the access checks not allowing the guest to write to the
* state field when SPSel indicates that it's being used as the stack
* pointer.
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
2015-03-17 19:19 ` [Qemu-devel] " Peter Maydell
@ 2015-03-17 19:22 ` Christoffer Dall
-1 siblings, 0 replies; 6+ messages in thread
From: Christoffer Dall @ 2015-03-17 19:22 UTC (permalink / raw)
To: Peter Maydell; +Cc: kvmarm, Greg Bellows, qemu-devel, patches
On Tue, Mar 17, 2015 at 07:19:35PM +0000, Peter Maydell wrote:
> The AArch64 SPSR_EL1 register is architecturally mandated to
> be mapped to the AArch32 SPSR_svc register. This means its
> state should live in QEMU's env->banked_spsr[1] field.
> Correct the buggy regdef that put it in banked_spsr[0] instead.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 10886c5..d77c6de 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2438,7 +2438,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
> .type = ARM_CP_ALIAS,
> .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
> - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
> + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
> /* We rely on the access checks not allowing the guest to write to the
> * state field when SPSel indicates that it's being used as the stack
> * pointer.
> --
> 1.9.1
>
Don't you need to change aarch64_banked_spsr_index() accordingly?
-Christoffer
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [Qemu-devel] [PATCH] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
@ 2015-03-17 19:22 ` Christoffer Dall
0 siblings, 0 replies; 6+ messages in thread
From: Christoffer Dall @ 2015-03-17 19:22 UTC (permalink / raw)
To: Peter Maydell; +Cc: kvmarm, Greg Bellows, Alex Bennée, qemu-devel, patches
On Tue, Mar 17, 2015 at 07:19:35PM +0000, Peter Maydell wrote:
> The AArch64 SPSR_EL1 register is architecturally mandated to
> be mapped to the AArch32 SPSR_svc register. This means its
> state should live in QEMU's env->banked_spsr[1] field.
> Correct the buggy regdef that put it in banked_spsr[0] instead.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 10886c5..d77c6de 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2438,7 +2438,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
> .type = ARM_CP_ALIAS,
> .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
> - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
> + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
> /* We rely on the access checks not allowing the guest to write to the
> * state field when SPSel indicates that it's being used as the stack
> * pointer.
> --
> 1.9.1
>
Don't you need to change aarch64_banked_spsr_index() accordingly?
-Christoffer
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
2015-03-17 19:22 ` [Qemu-devel] " Christoffer Dall
@ 2015-03-17 19:24 ` Peter Maydell
-1 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2015-03-17 19:24 UTC (permalink / raw)
To: Christoffer Dall
Cc: kvmarm@lists.cs.columbia.edu, Greg Bellows, QEMU Developers,
Patch Tracking
On 17 March 2015 at 19:22, Christoffer Dall <christoffer.dall@linaro.org> wrote:
> On Tue, Mar 17, 2015 at 07:19:35PM +0000, Peter Maydell wrote:
>> The AArch64 SPSR_EL1 register is architecturally mandated to
>> be mapped to the AArch32 SPSR_svc register. This means its
>> state should live in QEMU's env->banked_spsr[1] field.
>> Correct the buggy regdef that put it in banked_spsr[0] instead.
>>
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>> ---
>> target-arm/helper.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>> index 10886c5..d77c6de 100644
>> --- a/target-arm/helper.c
>> +++ b/target-arm/helper.c
>> @@ -2438,7 +2438,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>> { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
>> .type = ARM_CP_ALIAS,
>> .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
>> - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
>> + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
>> /* We rely on the access checks not allowing the guest to write to the
>> * state field when SPSel indicates that it's being used as the stack
>> * pointer.
>> --
>> 1.9.1
>>
>
> Don't you need to change aarch64_banked_spsr_index() accordingly?
We do, I had not noticed that bit of code :-)
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [Qemu-devel] [PATCH] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
@ 2015-03-17 19:24 ` Peter Maydell
0 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2015-03-17 19:24 UTC (permalink / raw)
To: Christoffer Dall
Cc: kvmarm@lists.cs.columbia.edu, Greg Bellows, Alex Bennée,
QEMU Developers, Patch Tracking
On 17 March 2015 at 19:22, Christoffer Dall <christoffer.dall@linaro.org> wrote:
> On Tue, Mar 17, 2015 at 07:19:35PM +0000, Peter Maydell wrote:
>> The AArch64 SPSR_EL1 register is architecturally mandated to
>> be mapped to the AArch32 SPSR_svc register. This means its
>> state should live in QEMU's env->banked_spsr[1] field.
>> Correct the buggy regdef that put it in banked_spsr[0] instead.
>>
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>> ---
>> target-arm/helper.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>> index 10886c5..d77c6de 100644
>> --- a/target-arm/helper.c
>> +++ b/target-arm/helper.c
>> @@ -2438,7 +2438,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>> { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
>> .type = ARM_CP_ALIAS,
>> .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
>> - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
>> + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
>> /* We rely on the access checks not allowing the guest to write to the
>> * state field when SPSel indicates that it's being used as the stack
>> * pointer.
>> --
>> 1.9.1
>>
>
> Don't you need to change aarch64_banked_spsr_index() accordingly?
We do, I had not noticed that bit of code :-)
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-03-17 19:24 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2015-03-17 19:19 [PATCH] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc) Peter Maydell
2015-03-17 19:19 ` [Qemu-devel] " Peter Maydell
2015-03-17 19:22 ` Christoffer Dall
2015-03-17 19:22 ` [Qemu-devel] " Christoffer Dall
2015-03-17 19:24 ` Peter Maydell
2015-03-17 19:24 ` [Qemu-devel] " Peter Maydell
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