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From: Andi Kleen <andi@firstfloor.org>
To: Kan Liang <kan.liang@intel.com>
Cc: a.p.zijlstra@chello.nl, linux-kernel@vger.kernel.org,
	mingo@kernel.org, acme@infradead.org, eranian@google.com,
	andi@firstfloor.org
Subject: Re: [PATCH V6 4/6] perf, x86: handle multiple records in PEBS buffer
Date: Thu, 9 Apr 2015 23:01:17 +0200	[thread overview]
Message-ID: <20150409210116.GX2366@two.firstfloor.org> (raw)
In-Reply-To: <1428597466-8154-5-git-send-email-kan.liang@intel.com>

> +	for_each_set_bit(bit, (unsigned long *)&pebs_status, 64) {
> +
> +		if (bit >= x86_pmu.max_pebs_events)
> +			clear_bit(bit, (unsigned long *)&pebs_status);
> +		else {
> +			event = cpuc->events[bit];
> +			WARN_ON_ONCE(!event);
> +
> +			if (!event->attr.precise_ip)
> +				clear_bit(bit, (unsigned long *)&pebs_status);

Precompute the mask of non pebs events first in the caller.
Then this function would be just a & ~mask

BTW clear_bit is atomic, if you're local you should always use
__clear_bit.


> +}
> +
> +static inline void *
> +get_next_pebs_record_by_bit(void *base, void *top, int bit)
> +{
> +	void *at;
> +	u64 pebs_status;
> +
> +	if (base == NULL)
> +		return NULL;
> +
> +	for (at = base; at < top; at += x86_pmu.pebs_record_size) {
> +		struct pebs_record_nhm *p = at;
> +
> +		if (p->status & (1 << bit)) {

Use test_bit.

> +
> +			if (p->status == (1 << bit))
> +				return at;
> +
> +			/* clear non-PEBS bit and re-check */
> +			pebs_status = nonpebs_bit_clear(p->status);
> +			if (pebs_status == (1 << bit))
> +				return at;
> +		}
> +	}
> +	return NULL;

-Andi

-- 
ak@linux.intel.com -- Speaking for myself only.

  reply	other threads:[~2015-04-09 21:01 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-09 16:37 [PATCH V6 0/6] large PEBS interrupt threshold Kan Liang
2015-04-09 16:37 ` [PATCH V6 1/6] perf, x86: use the PEBS auto reload mechanism when possible Kan Liang
2015-04-09 16:37 ` [PATCH V6 2/6] perf, x86: introduce setup_pebs_sample_data() Kan Liang
2015-04-09 16:37 ` [PATCH V6 3/6] perf, x86: large PEBS interrupt threshold Kan Liang
2015-04-15 17:14   ` Peter Zijlstra
2015-04-15 17:48     ` Liang, Kan
2015-04-15 18:10       ` Peter Zijlstra
2015-04-15 18:05   ` Peter Zijlstra
2015-04-15 18:35     ` Liang, Kan
2015-04-15 18:41       ` Peter Zijlstra
2015-04-16 18:45   ` Peter Zijlstra
2015-04-09 16:37 ` [PATCH V6 4/6] perf, x86: handle multiple records in PEBS buffer Kan Liang
2015-04-09 21:01   ` Andi Kleen [this message]
2015-04-15 18:28   ` Peter Zijlstra
2015-04-15 18:36   ` Peter Zijlstra
2015-04-16 12:53   ` Peter Zijlstra
2015-04-17  8:11     ` Peter Zijlstra
2015-04-17 12:50       ` Liang, Kan
2015-04-17 13:12         ` Peter Zijlstra
2015-04-17 14:19           ` Liang, Kan
2015-04-17 14:44             ` Peter Zijlstra
2015-04-17 18:20               ` Andi Kleen
2015-04-17 18:25                 ` Peter Zijlstra
2015-04-09 16:37 ` [PATCH V6 5/6] perf, x86: drain PEBS buffer during context switch Kan Liang
2015-04-09 16:37 ` [PATCH V6 6/6] perf, x86: enlarge PEBS buffer Kan Liang

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