Re: Fw: Re: [PATCH 3/3] drm/exynos: enable/disable blend based on pixel format

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Fri, Apr 17, 2015 at 02:55:57PM +0200, Tobias Jakobi wrote:
> Hello Joonyoung,
> 
> I thought about this some more.
> 
> 
> > Gesendet: Freitag, 17. April 2015 um 08:16 Uhr
> > Von: "Joonyoung Shim" <jy0922.shim@samsung.com>
> > An: "Gustavo Padovan" <gustavo@padovan.org>, 
> > linux-samsung-soc@vger.kernel.org
> > Cc: dri-devel@lists.freedesktop.org, inki.dae@samsung.com, "Gustavo
> > Padovan" <gustavo.padovan@collabora.co.uk>
> > Betreff: Re: [PATCH 3/3] drm/exynos: enable/disable blend based on 
> > pixel format
> > Hi Gustavo,
> > 
> > On 03/19/2015 11:27 PM, Gustavo Padovan wrote:
> >> From: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
> >> 
> >> Change the switch to use the pixel_format instead of bpp to figure out
> >> if we need to enable or disable the layer blending.
> >> 
> > 
> > The default concept is ok about enable or disable of pixel blending
> > feature by pixel_format, but it will make to possible blending with
> > background layer. I'm not sure whether it's proper or not.
> I think one of the reasons why this is currently causing confusion is 
> because the background layer is not exposed to userspace. So an idea 
> would be to expose BG as a normal DRM plane, with a background_rgb 
> propery.

Is it just a color? The plan is to expose that simply as a crtc
property. There have been some patches floating around for intel.
Not sure if those were cc:d to dri-devel properly.

> 
> Then we just need to keep track which planes are enabled.
> 
> E.g. if just the primary plane is enabled, then we ignore any alpha 
> pixelformat (in the sense that we map it to its non-alpha counterpart). 
> If another plane, which is located 'underneath', is enabled, then we 
> honor the alpha. This could then be the background plane.
> 
> 
> With best wishes,
> Tobias
> 
> 
> 
> > 
> > Thanks.
> > 
> >> Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
> >> ---
> >> drivers/gpu/drm/exynos/exynos_mixer.c | 29 
> >> +++++++++++++++++++++++++----
> >> 1 file changed, 25 insertions(+), 4 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c 
> >> b/drivers/gpu/drm/exynos/exynos_mixer.c
> >> index 7aff88f..0c54098 100644
> >> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> >> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> >> @@ -529,7 +529,7 @@ static void mixer_graph_buffer(struct 
> >> mixer_context *ctx, int win)
> >> unsigned int x_ratio, y_ratio;
> >> unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
> >> dma_addr_t dma_addr;
> >> - unsigned int fmt;
> >> + unsigned int fmt, blend;
> >> u32 val;
> >> 
> >> win_data = &ctx->win_data[win];
> >> @@ -539,15 +539,26 @@ static void mixer_graph_buffer(struct 
> >> mixer_context *ctx, int win)
> >> #define ARGB4444 6
> >> #define ARGB8888 7
> >> 
> >> - switch (win_data->bpp) {
> >> - case 16:
> >> + switch (win_data->pixel_format) {
> >> + case DRM_FORMAT_ARGB4444:
> >> fmt = ARGB4444;
> >> + blend = 1;
> >> break;
> >> - case 32:
> >> +
> >> + case DRM_FORMAT_ARGB8888:
> >> + fmt = ARGB8888;
> >> + blend = 1;
> >> + break;
> >> +
> >> + case DRM_FORMAT_XRGB8888:
> >> fmt = ARGB8888;
> >> + blend = 0;
> >> break;
> >> +
> >> default:
> >> fmt = ARGB8888;
> >> + blend = 0;
> >> + break;
> >> }
> >> 
> >> if (win_data->crtc_width != win_data->src_width ||
> >> @@ -586,6 +597,16 @@ static void mixer_graph_buffer(struct 
> >> mixer_context *ctx, int win)
> >> mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
> >> win_data->fb_pitch / (win_data->bpp >> 3));
> >> 
> >> + if (blend) {
> >> + val = MXR_GRP_CFG_BLEND_PRE_MUL;
> >> + val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
> >> + } else {
> >> + val = 0;
> >> + }
> >> + mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), val,
> >> + MXR_GRP_CFG_BLEND_PRE_MUL
> >> + | MXR_GRP_CFG_PIXEL_BLEND_EN);
> >> +
> >> /* setup display size */
> >> if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
> >> win == MIXER_DEFAULT_WIN) {
> >> 
> > 
> > --
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-- 
Ville Syrjälä
Intel OTC
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