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From: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
To: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
	Thierry Reding
	<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Alexandre Courbot
	<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	"linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
	Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	Ian Campbell
	<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
	Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	Samuel Ortiz <sameo-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Subject: Re: [PATCH V7 4/9] mfd: Add binding document for NVIDIA Tegra XUSB
Date: Wed, 29 Apr 2015 19:34:29 +0100	[thread overview]
Message-ID: <20150429183429.GB9169@x1> (raw)
In-Reply-To: <CAL1qeaFh5go_K0GnGXxU7KqjcgCm2kpUL5mVgGSYosPoXAXgpw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

On Wed, 29 Apr 2015, Andrew Bresticker wrote:

> Lee,
> 
> On Wed, Apr 29, 2015 at 2:25 AM, Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> > On Mon, 27 Apr 2015, Andrew Bresticker wrote:
> >
> >> Add a binding document for the XUSB host complex on NVIDIA Tegra124
> >> and later SoCs.  The XUSB host complex includes a mailbox for
> >> communication with the XUSB micro-controller and an xHCI host-controller.
> >>
> >> Signed-off-by: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> >> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> >> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> >> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> >> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> >> Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> >> Cc: Samuel Ortiz <sameo-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> >> Cc: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> >> ---
> >> New for v7.
> >> ---
> >>  .../bindings/mfd/nvidia,tegra124-xusb.txt          | 46 ++++++++++++++++++++++
> >>  1 file changed, 46 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >> new file mode 100644
> >> index 0000000..6a46680
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >> @@ -0,0 +1,46 @@
> >> +NVIDIA Tegra XUSB host copmlex
> >> +==============================
> >> +
> >> +The XUSB host complex on Tegra124 and later SoCs contains an xHCI host
> >> +controller and a mailbox for communication with the XUSB micro-controller.
> >> +
> >> +Required properties:
> >> +--------------------
> >> + - compatible: For Tegra124, must contain "nvidia,tegra124-xusb".
> >> +   Otherwise, must contain '"nvidia,<chip>-xusb", "nvidia,tegra124-xusb"'
> >> +   where <chip> is tegra132.
> >
> > Okay.  Why?
> 
> Why what?  This is the convention used for Tegra bindings and is also
> documented in Documentation/devicetree/bindings/submitting-patches.txt.
> See nvidia,tegra114-spi.txt and nvidia,tegra20-i2c.txt for other
> examples of this.

It seems strange to me that you'd mention two specific chips in one
compatible string.  What's the purpose of that?

> >> + - reg: Must contain register base and length for each register set listed
> >> +   in reg-names.
> >
> > You've mentioned 2 of the cells, what about the remaining 2?
> 
> The example given was for Tegra124, where there are two address cells
> and two size cells.

I don't get that.  How does that work?

> >> + - reg-names: Must include the following entries:
> >> +   - xhci
> >> +   - fpci
> >> +   - ipfs
> >> + - interrupts: Must contain an interrupt for each entry in interrupt-names.
> >> + - interrupt-names: Must include the following entries:
> >> +   - host
> >> +   - smi
> >> +   - pme
> >> +
> >> +Example:
> >> +--------
> >> +     usb@0,70090000 {
> >> +             compatible = "nvidia,tegra124-xusb";
> >> +             reg = <0x0 0x70090000 0x0 0x8000>,
> >> +                   <0x0 0x70098000 0x0 0x1000>,
> >> +                   <0x0 0x70099000 0x0 0x1000>;
> >> +             reg-names = "xhci", "fpci", "ipfs";
> >> +             interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> >> +                          <GIC_SPI 40 IRQ_TYPE_LEVEL_HGIH>,
> >> +                          <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> >> +             interrupt-names = "host", "smi", "pme";
> >
> > Are these resources used by both children?
> 
> Only the FPCI register set is shared.
> 
> > If not, place them into the children and ioremap() them from the
> > associated child drivers.
> 
> Ok.

Great.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

WARNING: multiple messages have this Message-ID (diff)
From: lee.jones@linaro.org (Lee Jones)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V7 4/9] mfd: Add binding document for NVIDIA Tegra XUSB
Date: Wed, 29 Apr 2015 19:34:29 +0100	[thread overview]
Message-ID: <20150429183429.GB9169@x1> (raw)
In-Reply-To: <CAL1qeaFh5go_K0GnGXxU7KqjcgCm2kpUL5mVgGSYosPoXAXgpw@mail.gmail.com>

On Wed, 29 Apr 2015, Andrew Bresticker wrote:

> Lee,
> 
> On Wed, Apr 29, 2015 at 2:25 AM, Lee Jones <lee.jones@linaro.org> wrote:
> > On Mon, 27 Apr 2015, Andrew Bresticker wrote:
> >
> >> Add a binding document for the XUSB host complex on NVIDIA Tegra124
> >> and later SoCs.  The XUSB host complex includes a mailbox for
> >> communication with the XUSB micro-controller and an xHCI host-controller.
> >>
> >> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> >> Cc: Rob Herring <robh+dt@kernel.org>
> >> Cc: Pawel Moll <pawel.moll@arm.com>
> >> Cc: Mark Rutland <mark.rutland@arm.com>
> >> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> >> Cc: Kumar Gala <galak@codeaurora.org>
> >> Cc: Samuel Ortiz <sameo@linux.intel.com>
> >> Cc: Lee Jones <lee.jones@linaro.org>
> >> ---
> >> New for v7.
> >> ---
> >>  .../bindings/mfd/nvidia,tegra124-xusb.txt          | 46 ++++++++++++++++++++++
> >>  1 file changed, 46 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >> new file mode 100644
> >> index 0000000..6a46680
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >> @@ -0,0 +1,46 @@
> >> +NVIDIA Tegra XUSB host copmlex
> >> +==============================
> >> +
> >> +The XUSB host complex on Tegra124 and later SoCs contains an xHCI host
> >> +controller and a mailbox for communication with the XUSB micro-controller.
> >> +
> >> +Required properties:
> >> +--------------------
> >> + - compatible: For Tegra124, must contain "nvidia,tegra124-xusb".
> >> +   Otherwise, must contain '"nvidia,<chip>-xusb", "nvidia,tegra124-xusb"'
> >> +   where <chip> is tegra132.
> >
> > Okay.  Why?
> 
> Why what?  This is the convention used for Tegra bindings and is also
> documented in Documentation/devicetree/bindings/submitting-patches.txt.
> See nvidia,tegra114-spi.txt and nvidia,tegra20-i2c.txt for other
> examples of this.

It seems strange to me that you'd mention two specific chips in one
compatible string.  What's the purpose of that?

> >> + - reg: Must contain register base and length for each register set listed
> >> +   in reg-names.
> >
> > You've mentioned 2 of the cells, what about the remaining 2?
> 
> The example given was for Tegra124, where there are two address cells
> and two size cells.

I don't get that.  How does that work?

> >> + - reg-names: Must include the following entries:
> >> +   - xhci
> >> +   - fpci
> >> +   - ipfs
> >> + - interrupts: Must contain an interrupt for each entry in interrupt-names.
> >> + - interrupt-names: Must include the following entries:
> >> +   - host
> >> +   - smi
> >> +   - pme
> >> +
> >> +Example:
> >> +--------
> >> +     usb at 0,70090000 {
> >> +             compatible = "nvidia,tegra124-xusb";
> >> +             reg = <0x0 0x70090000 0x0 0x8000>,
> >> +                   <0x0 0x70098000 0x0 0x1000>,
> >> +                   <0x0 0x70099000 0x0 0x1000>;
> >> +             reg-names = "xhci", "fpci", "ipfs";
> >> +             interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> >> +                          <GIC_SPI 40 IRQ_TYPE_LEVEL_HGIH>,
> >> +                          <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> >> +             interrupt-names = "host", "smi", "pme";
> >
> > Are these resources used by both children?
> 
> Only the FPCI register set is shared.
> 
> > If not, place them into the children and ioremap() them from the
> > associated child drivers.
> 
> Ok.

Great.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

WARNING: multiple messages have this Message-ID (diff)
From: Lee Jones <lee.jones@linaro.org>
To: Andrew Bresticker <abrestic@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Alexandre Courbot <gnurou@gmail.com>,
	"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
	"linux-usb@vger.kernel.org" <linux-usb@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Kumar Gala <galak@codeaurora.org>,
	Samuel Ortiz <sameo@linux.intel.com>
Subject: Re: [PATCH V7 4/9] mfd: Add binding document for NVIDIA Tegra XUSB
Date: Wed, 29 Apr 2015 19:34:29 +0100	[thread overview]
Message-ID: <20150429183429.GB9169@x1> (raw)
In-Reply-To: <CAL1qeaFh5go_K0GnGXxU7KqjcgCm2kpUL5mVgGSYosPoXAXgpw@mail.gmail.com>

On Wed, 29 Apr 2015, Andrew Bresticker wrote:

> Lee,
> 
> On Wed, Apr 29, 2015 at 2:25 AM, Lee Jones <lee.jones@linaro.org> wrote:
> > On Mon, 27 Apr 2015, Andrew Bresticker wrote:
> >
> >> Add a binding document for the XUSB host complex on NVIDIA Tegra124
> >> and later SoCs.  The XUSB host complex includes a mailbox for
> >> communication with the XUSB micro-controller and an xHCI host-controller.
> >>
> >> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> >> Cc: Rob Herring <robh+dt@kernel.org>
> >> Cc: Pawel Moll <pawel.moll@arm.com>
> >> Cc: Mark Rutland <mark.rutland@arm.com>
> >> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> >> Cc: Kumar Gala <galak@codeaurora.org>
> >> Cc: Samuel Ortiz <sameo@linux.intel.com>
> >> Cc: Lee Jones <lee.jones@linaro.org>
> >> ---
> >> New for v7.
> >> ---
> >>  .../bindings/mfd/nvidia,tegra124-xusb.txt          | 46 ++++++++++++++++++++++
> >>  1 file changed, 46 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >> new file mode 100644
> >> index 0000000..6a46680
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/mfd/nvidia,tegra124-xusb.txt
> >> @@ -0,0 +1,46 @@
> >> +NVIDIA Tegra XUSB host copmlex
> >> +==============================
> >> +
> >> +The XUSB host complex on Tegra124 and later SoCs contains an xHCI host
> >> +controller and a mailbox for communication with the XUSB micro-controller.
> >> +
> >> +Required properties:
> >> +--------------------
> >> + - compatible: For Tegra124, must contain "nvidia,tegra124-xusb".
> >> +   Otherwise, must contain '"nvidia,<chip>-xusb", "nvidia,tegra124-xusb"'
> >> +   where <chip> is tegra132.
> >
> > Okay.  Why?
> 
> Why what?  This is the convention used for Tegra bindings and is also
> documented in Documentation/devicetree/bindings/submitting-patches.txt.
> See nvidia,tegra114-spi.txt and nvidia,tegra20-i2c.txt for other
> examples of this.

It seems strange to me that you'd mention two specific chips in one
compatible string.  What's the purpose of that?

> >> + - reg: Must contain register base and length for each register set listed
> >> +   in reg-names.
> >
> > You've mentioned 2 of the cells, what about the remaining 2?
> 
> The example given was for Tegra124, where there are two address cells
> and two size cells.

I don't get that.  How does that work?

> >> + - reg-names: Must include the following entries:
> >> +   - xhci
> >> +   - fpci
> >> +   - ipfs
> >> + - interrupts: Must contain an interrupt for each entry in interrupt-names.
> >> + - interrupt-names: Must include the following entries:
> >> +   - host
> >> +   - smi
> >> +   - pme
> >> +
> >> +Example:
> >> +--------
> >> +     usb@0,70090000 {
> >> +             compatible = "nvidia,tegra124-xusb";
> >> +             reg = <0x0 0x70090000 0x0 0x8000>,
> >> +                   <0x0 0x70098000 0x0 0x1000>,
> >> +                   <0x0 0x70099000 0x0 0x1000>;
> >> +             reg-names = "xhci", "fpci", "ipfs";
> >> +             interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> >> +                          <GIC_SPI 40 IRQ_TYPE_LEVEL_HGIH>,
> >> +                          <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> >> +             interrupt-names = "host", "smi", "pme";
> >
> > Are these resources used by both children?
> 
> Only the FPCI register set is shared.
> 
> > If not, place them into the children and ioremap() them from the
> > associated child drivers.
> 
> Ok.

Great.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

  parent reply	other threads:[~2015-04-29 18:34 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-27 22:37 [PATCH V7 0/9] Tegra xHCI support Andrew Bresticker
2015-04-27 22:37 ` Andrew Bresticker
2015-04-27 22:37 ` Andrew Bresticker
2015-04-27 22:37 ` [PATCH V7 1/9] xhci: Set shared HCD's hcd_priv in xhci_gen_setup Andrew Bresticker
2015-04-27 22:37   ` Andrew Bresticker
     [not found] ` <1430174242-29465-1-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2015-04-27 22:37   ` [PATCH V7 2/9] mailbox: Make struct mbox_controller's ops field const Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
     [not found]     ` <1430174242-29465-3-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2015-04-28 16:49       ` Suman Anna
2015-04-28 16:49         ` Suman Anna
2015-04-28 16:49         ` Suman Anna
2015-04-27 22:37   ` [PATCH V7 3/9] mailbox: Fix up error handling in mbox_request_channel() Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
2015-04-28 16:42     ` Suman Anna
2015-04-28 16:42       ` Suman Anna
2015-04-28 16:42       ` Suman Anna
2015-04-27 22:37   ` [PATCH V7 4/9] mfd: Add binding document for NVIDIA Tegra XUSB Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
     [not found]     ` <1430174242-29465-5-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2015-04-29  9:25       ` Lee Jones
2015-04-29  9:25         ` Lee Jones
2015-04-29  9:25         ` Lee Jones
2015-04-29 17:02         ` Andrew Bresticker
2015-04-29 17:02           ` Andrew Bresticker
     [not found]           ` <CAL1qeaFh5go_K0GnGXxU7KqjcgCm2kpUL5mVgGSYosPoXAXgpw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-04-29 18:34             ` Lee Jones [this message]
2015-04-29 18:34               ` Lee Jones
2015-04-29 18:34               ` Lee Jones
2015-04-29 19:46               ` Andrew Bresticker
2015-04-29 19:46                 ` Andrew Bresticker
2015-04-29 19:46                 ` Andrew Bresticker
     [not found]                 ` <CAL1qeaEt9kGbcCfwqhVzwJxx9DvgOnjfU6C8MCH6t0vqwJK0WA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-04-30 10:06                   ` Lee Jones
2015-04-30 10:06                     ` Lee Jones
2015-04-30 10:06                     ` Lee Jones
2015-04-30 16:28                     ` Andrew Bresticker
2015-04-30 16:28                       ` Andrew Bresticker
2015-04-30 16:28                       ` Andrew Bresticker
2015-04-27 22:37   ` [PATCH V7 5/9] mfd: Add driver " Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
2015-04-29  9:23     ` Lee Jones
2015-04-29  9:23       ` Lee Jones
2015-04-29 17:59       ` Andrew Bresticker
2015-04-29 17:59         ` Andrew Bresticker
2015-04-29 17:59         ` Andrew Bresticker
2015-04-29 18:30         ` Lee Jones
2015-04-29 18:30           ` Lee Jones
2015-04-27 22:37   ` [PATCH V7 6/9] mailbox: Add NVIDIA Tegra XUSB mailbox binding Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
2015-04-27 22:37   ` [PATCH V7 7/9] mailbox: Add NVIDIA Tegra XUSB mailbox driver Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
2015-04-27 22:37   ` [PATCH V7 8/9] usb: Add NVIDIA Tegra xHCI controller binding Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
2015-04-27 22:37     ` Andrew Bresticker
2015-04-27 22:37 ` [PATCH V7 9/9] usb: xhci: Add NVIDIA Tegra xHCI host-controller driver Andrew Bresticker
2015-04-27 22:37   ` Andrew Bresticker

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