* [PATCH] drm/i915: clean up dsi pll calculation
@ 2015-05-07 14:14 Jani Nikula
2015-05-08 10:09 ` shuang.he
2015-05-12 11:29 ` Ville Syrjälä
0 siblings, 2 replies; 6+ messages in thread
From: Jani Nikula @ 2015-05-07 14:14 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Improve readability. No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
Cleaning up old branches... :)
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 52 ++++++++++++------------------------
1 file changed, 17 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 3622d0bafdf8..fc139946abee 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -162,53 +162,35 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
#endif
-static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
+static int dsi_calc_mnp(u32 target_dsi_clk, struct dsi_mnp *dsi_mnp)
{
u32 m, n, p;
- u32 ref_clk;
- u32 error;
- u32 tmp_error;
- int target_dsi_clk;
- int calc_dsi_clk;
- u32 calc_m;
- u32 calc_p;
+ u32 ref_clk = 25000;
+ u32 delta = target_dsi_clk;
+ u32 calc_m = 0;
+ u32 calc_p = 0;
u32 m_seed;
- /* dsi_clk is expected in KHZ */
- if (dsi_clk < 300000 || dsi_clk > 1150000) {
+ /* target_dsi_clk is expected in KHZ */
+ if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
DRM_ERROR("DSI CLK Out of Range\n");
return -ECHRNG;
}
- ref_clk = 25000;
- target_dsi_clk = dsi_clk;
- error = 0xFFFFFFFF;
- tmp_error = 0xFFFFFFFF;
- calc_m = 0;
- calc_p = 0;
-
- for (m = 62; m <= 92; m++) {
- for (p = 2; p <= 6; p++) {
- /* Find the optimal m and p divisors
- with minimal error +/- the required clock */
- calc_dsi_clk = (m * ref_clk) / p;
- if (calc_dsi_clk == target_dsi_clk) {
- calc_m = m;
- calc_p = p;
- error = 0;
- break;
- } else
- tmp_error = abs(target_dsi_clk - calc_dsi_clk);
-
- if (tmp_error < error) {
- error = tmp_error;
+ for (m = 62; m <= 92 && delta; m++) {
+ for (p = 2; p <= 6 && delta; p++) {
+ /*
+ * Find the optimal m and p divisors with minimal delta
+ * +/- the required clock
+ */
+ int calc_dsi_clk = (m * ref_clk) / p;
+ u32 d = abs(target_dsi_clk - calc_dsi_clk);
+ if (d < delta) {
+ delta = d;
calc_m = m;
calc_p = p;
}
}
-
- if (error == 0)
- break;
}
m_seed = lfsr_converts[calc_m - 62];
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: clean up dsi pll calculation
2015-05-07 14:14 [PATCH] drm/i915: clean up dsi pll calculation Jani Nikula
@ 2015-05-08 10:09 ` shuang.he
2015-05-12 11:29 ` Ville Syrjälä
1 sibling, 0 replies; 6+ messages in thread
From: shuang.he @ 2015-05-08 10:09 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, jani.nikula
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6346
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 282/282 282/282
SNB 316/316 316/316
IVB 342/342 342/342
BYT 286/286 286/286
BDW 321/321 321/321
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
Note: You need to pay more attention to line start with '*'
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: clean up dsi pll calculation
2015-05-07 14:14 [PATCH] drm/i915: clean up dsi pll calculation Jani Nikula
2015-05-08 10:09 ` shuang.he
@ 2015-05-12 11:29 ` Ville Syrjälä
2015-05-12 12:23 ` Jani Nikula
1 sibling, 1 reply; 6+ messages in thread
From: Ville Syrjälä @ 2015-05-12 11:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, May 07, 2015 at 05:14:17PM +0300, Jani Nikula wrote:
> Improve readability. No functional changes.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> ---
>
> Cleaning up old branches... :)
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c | 52 ++++++++++++------------------------
> 1 file changed, 17 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 3622d0bafdf8..fc139946abee 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -162,53 +162,35 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
>
> #endif
>
> -static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> +static int dsi_calc_mnp(u32 target_dsi_clk, struct dsi_mnp *dsi_mnp)
> {
> u32 m, n, p;
> - u32 ref_clk;
> - u32 error;
> - u32 tmp_error;
> - int target_dsi_clk;
> - int calc_dsi_clk;
> - u32 calc_m;
> - u32 calc_p;
> + u32 ref_clk = 25000;
> + u32 delta = target_dsi_clk;
> + u32 calc_m = 0;
> + u32 calc_p = 0;
> u32 m_seed;
>
> - /* dsi_clk is expected in KHZ */
> - if (dsi_clk < 300000 || dsi_clk > 1150000) {
> + /* target_dsi_clk is expected in KHZ */
> + if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
> DRM_ERROR("DSI CLK Out of Range\n");
> return -ECHRNG;
> }
>
> - ref_clk = 25000;
> - target_dsi_clk = dsi_clk;
> - error = 0xFFFFFFFF;
> - tmp_error = 0xFFFFFFFF;
> - calc_m = 0;
> - calc_p = 0;
> -
> - for (m = 62; m <= 92; m++) {
> - for (p = 2; p <= 6; p++) {
> - /* Find the optimal m and p divisors
> - with minimal error +/- the required clock */
> - calc_dsi_clk = (m * ref_clk) / p;
> - if (calc_dsi_clk == target_dsi_clk) {
> - calc_m = m;
> - calc_p = p;
> - error = 0;
> - break;
> - } else
> - tmp_error = abs(target_dsi_clk - calc_dsi_clk);
> -
> - if (tmp_error < error) {
> - error = tmp_error;
> + for (m = 62; m <= 92 && delta; m++) {
> + for (p = 2; p <= 6 && delta; p++) {
> + /*
> + * Find the optimal m and p divisors with minimal delta
> + * +/- the required clock
> + */
> + int calc_dsi_clk = (m * ref_clk) / p;
> + u32 d = abs(target_dsi_clk - calc_dsi_clk);
'target_dsi_clk - calc_dsi_clk' is going to be unsigned, so this is
still a bit confusing. abs() does stick that into a signed int before
comparing it, so it should just work, but still might be sensible to
make target_dsi_clk signed.
Also perhaps s/u32/unsigned int/ (or maybe just use int) all over?
> + if (d < delta) {
> + delta = d;
> calc_m = m;
> calc_p = p;
> }
> }
> -
> - if (error == 0)
> - break;
> }
>
> m_seed = lfsr_converts[calc_m - 62];
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] drm/i915: clean up dsi pll calculation
2015-05-12 11:29 ` Ville Syrjälä
@ 2015-05-12 12:23 ` Jani Nikula
2015-05-12 12:28 ` Ville Syrjälä
0 siblings, 1 reply; 6+ messages in thread
From: Jani Nikula @ 2015-05-12 12:23 UTC (permalink / raw)
To: Ville Syrjälä, Jani Nikula; +Cc: intel-gfx
Improve readability. No functional changes.
v2: use more rational types (Ville)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 53 ++++++++++++------------------------
1 file changed, 17 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 3622d0bafdf8..cfd527765156 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -162,53 +162,34 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
#endif
-static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
+static int dsi_calc_mnp(int target_dsi_clk, struct dsi_mnp *dsi_mnp)
{
- u32 m, n, p;
- u32 ref_clk;
- u32 error;
- u32 tmp_error;
- int target_dsi_clk;
- int calc_dsi_clk;
- u32 calc_m;
- u32 calc_p;
+ unsigned int calc_m = 0, calc_p = 0;
+ unsigned int m, n, p;
+ int ref_clk = 25000;
+ int delta = target_dsi_clk;
u32 m_seed;
- /* dsi_clk is expected in KHZ */
- if (dsi_clk < 300000 || dsi_clk > 1150000) {
+ /* target_dsi_clk is expected in kHz */
+ if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
DRM_ERROR("DSI CLK Out of Range\n");
return -ECHRNG;
}
- ref_clk = 25000;
- target_dsi_clk = dsi_clk;
- error = 0xFFFFFFFF;
- tmp_error = 0xFFFFFFFF;
- calc_m = 0;
- calc_p = 0;
-
- for (m = 62; m <= 92; m++) {
- for (p = 2; p <= 6; p++) {
- /* Find the optimal m and p divisors
- with minimal error +/- the required clock */
- calc_dsi_clk = (m * ref_clk) / p;
- if (calc_dsi_clk == target_dsi_clk) {
- calc_m = m;
- calc_p = p;
- error = 0;
- break;
- } else
- tmp_error = abs(target_dsi_clk - calc_dsi_clk);
-
- if (tmp_error < error) {
- error = tmp_error;
+ for (m = 62; m <= 92 && delta; m++) {
+ for (p = 2; p <= 6 && delta; p++) {
+ /*
+ * Find the optimal m and p divisors with minimal delta
+ * +/- the required clock
+ */
+ int calc_dsi_clk = (m * ref_clk) / p;
+ int d = abs(target_dsi_clk - calc_dsi_clk);
+ if (d < delta) {
+ delta = d;
calc_m = m;
calc_p = p;
}
}
-
- if (error == 0)
- break;
}
m_seed = lfsr_converts[calc_m - 62];
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: clean up dsi pll calculation
2015-05-12 12:23 ` Jani Nikula
@ 2015-05-12 12:28 ` Ville Syrjälä
2015-05-12 13:09 ` Daniel Vetter
0 siblings, 1 reply; 6+ messages in thread
From: Ville Syrjälä @ 2015-05-12 12:28 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, May 12, 2015 at 03:23:09PM +0300, Jani Nikula wrote:
> Improve readability. No functional changes.
>
> v2: use more rational types (Ville)
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks OK to me.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c | 53 ++++++++++++------------------------
> 1 file changed, 17 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 3622d0bafdf8..cfd527765156 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -162,53 +162,34 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
>
> #endif
>
> -static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> +static int dsi_calc_mnp(int target_dsi_clk, struct dsi_mnp *dsi_mnp)
> {
> - u32 m, n, p;
> - u32 ref_clk;
> - u32 error;
> - u32 tmp_error;
> - int target_dsi_clk;
> - int calc_dsi_clk;
> - u32 calc_m;
> - u32 calc_p;
> + unsigned int calc_m = 0, calc_p = 0;
> + unsigned int m, n, p;
> + int ref_clk = 25000;
> + int delta = target_dsi_clk;
> u32 m_seed;
>
> - /* dsi_clk is expected in KHZ */
> - if (dsi_clk < 300000 || dsi_clk > 1150000) {
> + /* target_dsi_clk is expected in kHz */
> + if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
> DRM_ERROR("DSI CLK Out of Range\n");
> return -ECHRNG;
> }
>
> - ref_clk = 25000;
> - target_dsi_clk = dsi_clk;
> - error = 0xFFFFFFFF;
> - tmp_error = 0xFFFFFFFF;
> - calc_m = 0;
> - calc_p = 0;
> -
> - for (m = 62; m <= 92; m++) {
> - for (p = 2; p <= 6; p++) {
> - /* Find the optimal m and p divisors
> - with minimal error +/- the required clock */
> - calc_dsi_clk = (m * ref_clk) / p;
> - if (calc_dsi_clk == target_dsi_clk) {
> - calc_m = m;
> - calc_p = p;
> - error = 0;
> - break;
> - } else
> - tmp_error = abs(target_dsi_clk - calc_dsi_clk);
> -
> - if (tmp_error < error) {
> - error = tmp_error;
> + for (m = 62; m <= 92 && delta; m++) {
> + for (p = 2; p <= 6 && delta; p++) {
> + /*
> + * Find the optimal m and p divisors with minimal delta
> + * +/- the required clock
> + */
> + int calc_dsi_clk = (m * ref_clk) / p;
> + int d = abs(target_dsi_clk - calc_dsi_clk);
> + if (d < delta) {
> + delta = d;
> calc_m = m;
> calc_p = p;
> }
> }
> -
> - if (error == 0)
> - break;
> }
>
> m_seed = lfsr_converts[calc_m - 62];
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: clean up dsi pll calculation
2015-05-12 12:28 ` Ville Syrjälä
@ 2015-05-12 13:09 ` Daniel Vetter
0 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2015-05-12 13:09 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Jani Nikula, intel-gfx
On Tue, May 12, 2015 at 03:28:41PM +0300, Ville Syrjälä wrote:
> On Tue, May 12, 2015 at 03:23:09PM +0300, Jani Nikula wrote:
> > Improve readability. No functional changes.
> >
> > v2: use more rational types (Ville)
> >
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Looks OK to me.
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-05-12 13:07 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2015-05-07 14:14 [PATCH] drm/i915: clean up dsi pll calculation Jani Nikula
2015-05-08 10:09 ` shuang.he
2015-05-12 11:29 ` Ville Syrjälä
2015-05-12 12:23 ` Jani Nikula
2015-05-12 12:28 ` Ville Syrjälä
2015-05-12 13:09 ` Daniel Vetter
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