From: Michael Turquette <mturquette@linaro.org>
To: Sergej Sawazki <ce3a@gmx.de>,
sboyd@codeaurora.org, sebastian.hesselbarth@gmail.com,
mwelling@ieee.org, moinejf@free.fr
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
"Sergej Sawazki" <ce3a@gmx.de>
Subject: Re: [PATCH 0/2] clk: si5351: Multisynth 6-7 fixes
Date: Tue, 12 May 2015 16:38:34 -0700 [thread overview]
Message-ID: <20150512233834.16410.23856@quantum> (raw)
In-Reply-To: <1431333859-7224-1-git-send-email-ce3a@gmx.de>
Quoting Sergej Sawazki (2015-05-11 01:44:19)
> The second synthesis stage in the Si5351 clock generator consists of six
> *fractional* multisynth dividers (MS0 .. MS5) and two *even-integer* =
> dividers (MS6 and MS7). The current si5351 driver implementation does
> not handle MS6 and MS7 correctly, this leads to wrong rates on output 6 =
> and 7. This patch series fixes that.
> =
> Patch 1 fixes the divider calculation for multisynth 6 and 7.
> =
> Patch 2 fixes the divider re-calculation for multisynth 6 and 7.
> =
> Info: Base on branch 'clk-fixes'.
> =
> Sergej Sawazki (2):
> clk: si5351: fix .round_rate for multisynth 6-7
> clk: si5351: fix .recalc_rate for multisynth 6-7
Applied both patches to clk-next.
Regards,
Mike
> =
> drivers/clk/clk-si5351.c | 26 +++++++++++++++++++-------
> 1 file changed, 19 insertions(+), 7 deletions(-)
> =
> -- =
> 1.9.1
>=20
WARNING: multiple messages have this Message-ID (diff)
From: Michael Turquette <mturquette@linaro.org>
To: Sergej Sawazki <ce3a@gmx.de>,
sboyd@codeaurora.org, sebastian.hesselbarth@gmail.com,
mwelling@ieee.org, moinejf@free.fr
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
"Sergej Sawazki" <ce3a@gmx.de>
Subject: Re: [PATCH 0/2] clk: si5351: Multisynth 6-7 fixes
Date: Tue, 12 May 2015 16:38:34 -0700 [thread overview]
Message-ID: <20150512233834.16410.23856@quantum> (raw)
In-Reply-To: <1431333859-7224-1-git-send-email-ce3a@gmx.de>
Quoting Sergej Sawazki (2015-05-11 01:44:19)
> The second synthesis stage in the Si5351 clock generator consists of six
> *fractional* multisynth dividers (MS0 .. MS5) and two *even-integer*
> dividers (MS6 and MS7). The current si5351 driver implementation does
> not handle MS6 and MS7 correctly, this leads to wrong rates on output 6
> and 7. This patch series fixes that.
>
> Patch 1 fixes the divider calculation for multisynth 6 and 7.
>
> Patch 2 fixes the divider re-calculation for multisynth 6 and 7.
>
> Info: Base on branch 'clk-fixes'.
>
> Sergej Sawazki (2):
> clk: si5351: fix .round_rate for multisynth 6-7
> clk: si5351: fix .recalc_rate for multisynth 6-7
Applied both patches to clk-next.
Regards,
Mike
>
> drivers/clk/clk-si5351.c | 26 +++++++++++++++++++-------
> 1 file changed, 19 insertions(+), 7 deletions(-)
>
> --
> 1.9.1
>
next prev parent reply other threads:[~2015-05-12 23:38 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-11 8:44 [PATCH 0/2] clk: si5351: Multisynth 6-7 fixes Sergej Sawazki
2015-05-12 23:38 ` Michael Turquette [this message]
2015-05-12 23:38 ` Michael Turquette
2015-05-15 9:25 ` Sebastian Hesselbarth
2015-05-16 10:13 ` Sergej Sawazki
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