From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Chen-Yu Tsai <wens@csie.org>
Cc: Mike Turquette <mturquette@linaro.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Emilio Lopez <emilio@elopez.com.ar>,
Hans de Goede <hdegoede@redhat.com>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-clk <linux-clk@vger.kernel.org>
Subject: Re: [PATCH 4/8] clk: sunxi: codec clock support
Date: Fri, 15 May 2015 09:46:06 +0200 [thread overview]
Message-ID: <20150515074606.GS4004@lukather> (raw)
In-Reply-To: <CAGb2v672-fdVi1iC=OTmYtY+rkzd95-KuVHZKAKA0peNvqBf2Q@mail.gmail.com>
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On Thu, May 14, 2015 at 07:03:07PM +0800, Chen-Yu Tsai wrote:
> On Sat, May 2, 2015 at 7:24 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > From: Emilio López <emilio@elopez.com.ar>
> >
> > The codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as
> > parent. Add a driver for such a clock.
> >
> > Signed-off-by: Emilio López <emilio@elopez.com.ar>
> > Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > drivers/clk/sunxi/Makefile | 1 +
> > drivers/clk/sunxi/clk-a10-codec.c | 45 +++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 46 insertions(+)
> > create mode 100644 drivers/clk/sunxi/clk-a10-codec.c
> >
> > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> > index eb36c38d4120..6fa845e13067 100644
> > --- a/drivers/clk/sunxi/Makefile
> > +++ b/drivers/clk/sunxi/Makefile
> > @@ -3,6 +3,7 @@
> > #
> >
> > obj-y += clk-sunxi.o clk-factors.o
> > +obj-y += clk-a10-codec.o
> > obj-y += clk-a10-hosc.o
> > obj-y += clk-a10-pll2.o
> > obj-y += clk-a20-gmac.o
> > diff --git a/drivers/clk/sunxi/clk-a10-codec.c b/drivers/clk/sunxi/clk-a10-codec.c
> > new file mode 100644
> > index 000000000000..aaeccf8cde39
> > --- /dev/null
> > +++ b/drivers/clk/sunxi/clk-a10-codec.c
> > @@ -0,0 +1,45 @@
> > +/*
> > + * Copyright 2013 Emilio López
> > + *
> > + * Emilio López <emilio@elopez.com.ar>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/clkdev.h>
>
> This one is not needed.
Right, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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WARNING: multiple messages have this Message-ID (diff)
From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/8] clk: sunxi: codec clock support
Date: Fri, 15 May 2015 09:46:06 +0200 [thread overview]
Message-ID: <20150515074606.GS4004@lukather> (raw)
In-Reply-To: <CAGb2v672-fdVi1iC=OTmYtY+rkzd95-KuVHZKAKA0peNvqBf2Q@mail.gmail.com>
On Thu, May 14, 2015 at 07:03:07PM +0800, Chen-Yu Tsai wrote:
> On Sat, May 2, 2015 at 7:24 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > From: Emilio L?pez <emilio@elopez.com.ar>
> >
> > The codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as
> > parent. Add a driver for such a clock.
> >
> > Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
> > Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > drivers/clk/sunxi/Makefile | 1 +
> > drivers/clk/sunxi/clk-a10-codec.c | 45 +++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 46 insertions(+)
> > create mode 100644 drivers/clk/sunxi/clk-a10-codec.c
> >
> > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> > index eb36c38d4120..6fa845e13067 100644
> > --- a/drivers/clk/sunxi/Makefile
> > +++ b/drivers/clk/sunxi/Makefile
> > @@ -3,6 +3,7 @@
> > #
> >
> > obj-y += clk-sunxi.o clk-factors.o
> > +obj-y += clk-a10-codec.o
> > obj-y += clk-a10-hosc.o
> > obj-y += clk-a10-pll2.o
> > obj-y += clk-a20-gmac.o
> > diff --git a/drivers/clk/sunxi/clk-a10-codec.c b/drivers/clk/sunxi/clk-a10-codec.c
> > new file mode 100644
> > index 000000000000..aaeccf8cde39
> > --- /dev/null
> > +++ b/drivers/clk/sunxi/clk-a10-codec.c
> > @@ -0,0 +1,45 @@
> > +/*
> > + * Copyright 2013 Emilio L?pez
> > + *
> > + * Emilio L?pez <emilio@elopez.com.ar>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/clkdev.h>
>
> This one is not needed.
Right, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2015-05-15 7:46 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-02 11:24 [PATCH 0/8] clk: sunxi: Add support for the Audio PLL Maxime Ripard
2015-05-02 11:24 ` Maxime Ripard
2015-05-02 11:24 ` [PATCH 1/8] clk: sunxi: factors: Add m_start parameters Maxime Ripard
2015-05-02 11:24 ` Maxime Ripard
2015-05-14 9:12 ` Chen-Yu Tsai
2015-05-14 9:12 ` Chen-Yu Tsai
2015-05-15 7:43 ` Maxime Ripard
2015-05-15 7:43 ` Maxime Ripard
2015-05-15 7:48 ` Chen-Yu Tsai
2015-05-15 7:48 ` Chen-Yu Tsai
2015-05-15 8:05 ` Maxime Ripard
2015-05-15 8:05 ` Maxime Ripard
2015-05-15 9:11 ` Chen-Yu Tsai
2015-05-15 9:11 ` Chen-Yu Tsai
2015-05-15 14:21 ` Maxime Ripard
2015-05-15 14:21 ` Maxime Ripard
2015-05-02 11:24 ` [PATCH 2/8] clk: sunxi: factors: Add a parameter for N and M zeros Maxime Ripard
2015-05-02 11:24 ` Maxime Ripard
2015-05-02 11:24 ` [PATCH 3/8] clk: sunxi: Add a driver for the PLL2 Maxime Ripard
2015-05-02 11:24 ` Maxime Ripard
2015-05-14 9:43 ` Chen-Yu Tsai
2015-05-14 9:43 ` Chen-Yu Tsai
2015-05-15 7:45 ` Maxime Ripard
2015-05-15 7:45 ` Maxime Ripard
2015-05-15 9:15 ` Chen-Yu Tsai
2015-05-15 9:15 ` Chen-Yu Tsai
2015-05-15 14:44 ` Maxime Ripard
2015-05-15 14:44 ` Maxime Ripard
2015-05-19 7:58 ` Chen-Yu Tsai
2015-05-19 7:58 ` Chen-Yu Tsai
2015-05-19 20:53 ` Maxime Ripard
2015-05-19 20:53 ` Maxime Ripard
2015-05-02 11:24 ` [PATCH 4/8] clk: sunxi: codec clock support Maxime Ripard
2015-05-02 11:24 ` Maxime Ripard
2015-05-14 11:03 ` Chen-Yu Tsai
2015-05-14 11:03 ` Chen-Yu Tsai
2015-05-15 7:46 ` Maxime Ripard [this message]
2015-05-15 7:46 ` Maxime Ripard
2015-05-02 11:24 ` [PATCH 5/8] clk: sunxi: mod1 " Maxime Ripard
2015-05-02 11:24 ` Maxime Ripard
2015-05-14 13:43 ` Chen-Yu Tsai
2015-05-14 13:43 ` Chen-Yu Tsai
2015-05-15 7:41 ` Maxime Ripard
2015-05-15 7:41 ` Maxime Ripard
2015-05-02 11:24 ` [PATCH 6/8] ARM: sunxi: Add PLL2 support Maxime Ripard
2015-05-02 11:24 ` Maxime Ripard
2015-05-02 11:24 ` [PATCH 7/8] ARM: sunxi: Add codec clock support Maxime Ripard
2015-05-02 11:24 ` Maxime Ripard
2015-05-14 12:43 ` Chen-Yu Tsai
2015-05-14 12:43 ` Chen-Yu Tsai
2015-05-02 11:24 ` [PATCH 8/8] ARM: sun7i: Add mod1 clock nodes Maxime Ripard
2015-05-02 11:24 ` Maxime Ripard
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