All of lore.kernel.org
 help / color / mirror / Atom feed
From: Matt Fleming <matt@codeblueprint.co.uk>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Vikas Shivappa <vikas.shivappa@linux.intel.com>,
	x86@kernel.org, Matt Fleming <matt.fleming@intel.com>,
	Will Auld <will.auld@intel.com>,
	Kanaka Juvva <kanaka.d.juvva@intel.com>
Subject: Re: [patch 6/6] x86, perf, cqm: Add storage for closid and cleanup struct intel_pqr_state
Date: Tue, 19 May 2015 12:54:57 +0100	[thread overview]
Message-ID: <20150519115457.GF17401@codeblueprint.co.uk> (raw)
In-Reply-To: <20150518235150.240899319@linutronix.de>

On Tue, 19 May, at 12:00:58AM, Thomas Gleixner wrote:
> closid (CLass Of Service ID) is used for the Class based Cache
> Allocation Technology (CAT). Add explicit storage to the per cpu cache
> for it, so it can be used later with the CAT support (requires to move
> the per cpu data).
> 
> While at it:
> 
>  - Rename the structure to intel_pqr_state which reflects the actual
>    purpose of the struct: Cache values which go into the PQR MSR
> 
>  - Rename 'cnt' to rmid_usecnt which reflects the actual purpose of
>    the counter.
> 
>  - Document the structure and the struct members.
> 
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> ---
>  arch/x86/kernel/cpu/perf_event_intel_cqm.c |   50 +++++++++++++++--------------
>  1 file changed, 27 insertions(+), 23 deletions(-)
> 
> Index: linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c
> ===================================================================
> --- linux.orig/arch/x86/kernel/cpu/perf_event_intel_cqm.c
> +++ linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c
> @@ -16,18 +16,32 @@
>  static unsigned int cqm_max_rmid = -1;
>  static unsigned int cqm_l3_scale; /* supposedly cacheline size */
>  
> -struct intel_cqm_state {
> +/**
> + * struct intel_pqr_state - State cache for the PQR MSR
> + * @rmid:	The cached Resource Monitoring ID
> + * @closid:	The cached Class Of Service ID
> + * @usecnt:	The usage counter for rmid
> + *

Typo? Should be @rmid_usecnt.

Otherwise,

Acked-by: Matt Fleming <matt.fleming@intel.com>

-- 
Matt Fleming, Intel Open Source Technology Center

  reply	other threads:[~2015-05-19 11:55 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-19  0:00 [patch 0/6] x86, perf, cqm: Cleanups and preparation for RDT/CAT Thomas Gleixner
2015-05-19  0:00 ` [patch 1/6] x86, perf, cqm: Document PQR MSR abuse Thomas Gleixner
2015-05-19 11:53   ` Matt Fleming
2015-05-27 10:02   ` [tip:perf/core] perf/x86/intel/cqm: " tip-bot for Thomas Gleixner
2015-05-19  0:00 ` [patch 2/6] x86, perf, cqm: Use proper data type Thomas Gleixner
2015-05-19  8:58   ` Matt Fleming
2015-05-19 13:03     ` Thomas Gleixner
2015-05-27 10:03   ` [tip:perf/core] perf/x86/intel/cqm: Use proper data types tip-bot for Thomas Gleixner
2015-05-19  0:00 ` [patch 3/6] x86, perf, cqm: Remove pointless spinlock from state cache Thomas Gleixner
2015-05-19  9:13   ` Matt Fleming
2015-05-19 10:51     ` Peter Zijlstra
2015-05-27 10:03   ` [tip:perf/core] perf/x86/intel/cqm: " tip-bot for Thomas Gleixner
2015-06-05 18:13   ` [patch 3/6] x86, perf, cqm: " Juvva, Kanaka D
2015-05-19  0:00 ` [patch 4/6] x86, perf, cqm: Avoid pointless msr write Thomas Gleixner
2015-05-19  9:17   ` Matt Fleming
2015-05-27 10:03   ` [tip:perf/core] perf/x86/intel/cqm: Avoid pointless MSR write tip-bot for Thomas Gleixner
2015-05-19  0:00 ` [patch 5/6] x86, perf, cqm: Remove useless wrapper function Thomas Gleixner
2015-05-19  9:18   ` Matt Fleming
2015-05-27 10:04   ` [tip:perf/core] perf/x86/intel/cqm: " tip-bot for Thomas Gleixner
2015-05-19  0:00 ` [patch 6/6] x86, perf, cqm: Add storage for closid and cleanup struct intel_pqr_state Thomas Gleixner
2015-05-19 11:54   ` Matt Fleming [this message]
2015-05-19 12:59     ` Thomas Gleixner
2015-05-27 10:04   ` [tip:perf/core] perf/x86/intel/cqm: Add storage for 'closid' and clean up 'struct intel_pqr_state' tip-bot for Thomas Gleixner
2015-05-19  7:42 ` [patch 0/6] x86, perf, cqm: Cleanups and preparation for RDT/CAT Peter Zijlstra

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20150519115457.GF17401@codeblueprint.co.uk \
    --to=matt@codeblueprint.co.uk \
    --cc=kanaka.d.juvva@intel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=matt.fleming@intel.com \
    --cc=peterz@infradead.org \
    --cc=tglx@linutronix.de \
    --cc=vikas.shivappa@linux.intel.com \
    --cc=will.auld@intel.com \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.