From: Stephen Boyd <sboyd@codeaurora.org>
To: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org, Lars-Peter Clausen <lars@metafoo.de>,
Mike Turquette <mturquette@linaro.org>,
linux-clk@vger.kernel.org
Subject: Re: [PATCH v4 25/37] clk: ingenic: add driver for Ingenic SoC CGU clocks
Date: Wed, 20 May 2015 16:16:44 -0700 [thread overview]
Message-ID: <20150520231644.GZ31753@codeaurora.org> (raw)
In-Reply-To: <1429881457-16016-26-git-send-email-paul.burton@imgtec.com>
On 04/24, Paul Burton wrote:
> +
> +static unsigned long
> +ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
> + struct ingenic_cgu *cgu = ingenic_clk->cgu;
> + const struct ingenic_cgu_clk_info *clk_info;
> + const struct ingenic_cgu_pll_info *pll_info;
> + unsigned m, n, od_enc, od;
> + bool bypass, enable;
> + unsigned long flags;
> + u32 ctl;
> +
> + clk_info = &cgu->clock_info[ingenic_clk->idx];
> + BUG_ON(clk_info->type != CGU_CLK_PLL);
> + pll_info = &clk_info->pll;
> +
> + spin_lock_irqsave(&cgu->lock, flags);
> + ctl = readl(cgu->base + pll_info->reg);
> + spin_unlock_irqrestore(&cgu->lock, flags);
> +
> + m = ((ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0));
> + m += pll_info->m_offset;
> + n = ((ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0));
Nitpick: Some unnecessary () here.
> + n += pll_info->n_offset;
> + od_enc = ctl >> pll_info->od_shift;
> + od_enc &= GENMASK(pll_info->od_bits - 1, 0);
> + bypass = !!(ctl & BIT(pll_info->bypass_bit));
> + enable = !!(ctl & BIT(pll_info->enable_bit));
> +
> + if (bypass)
> + return parent_rate;
> +
> + if (!enable)
> + return 0;
> +
> + for (od = 0; od < pll_info->od_max; od++) {
> + if (pll_info->od_encoding[od] == od_enc)
> + break;
> + }
> + BUG_ON(od == pll_info->od_max);
> + od++;
> +
> + return div_u64((u64)parent_rate * m, n * od);
> +
[...]
> +
> +/*
> + * Setup functions.
> + */
> +
> +static int register_clock(struct ingenic_cgu *cgu, unsigned idx)
Please namespace this. It's too generic. igenic_register_clk()?
> +{
> + const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx];
> + struct clk_init_data clk_init;
> + struct ingenic_clk *ingenic_clk = NULL;
[...]
> +
> +
> +/**
> + * ingenic_cgu_register_clocks() - Registers the clocks
> + * @cgu: pointer to cgu data
> + *
> + * Register the clocks described by the CGU with the common clock framework.
> + *
> + * Return: 1 on success or -errno if unsuccesful.
It looks like it returns 0 instead of 1 on success?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-05-20 23:16 UTC|newest]
Thread overview: 119+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-24 13:17 [PATCH v4 00/37] JZ4780 & CI20 support Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 01/37] devicetree/bindings: add Ingenic Semiconductor vendor prefix Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 02/37] devicetree/bindings: add Qi Hardware " Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 03/37] MIPS: JZ4740: introduce CONFIG_MACH_INGENIC Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 04/37] MIPS: ingenic: add newer vendor IDs Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 05/37] MIPS: JZ4740: require & include DT Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 06/37] MIPS: irq_cpu: declare irqchip table entry Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 07/37] MIPS: JZ4740: probe CPU interrupt controller via DT Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 08/37] MIPS: JZ4740: use generic plat_irq_dispatch Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 09/37] MIPS: JZ4740: move arch_init_irq out of arch/mips/jz4740/irq.c Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 10/37] devicetree: document Ingenic SoC interrupt controller binding Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 11/37] MIPS: JZ4740: probe interrupt controller via DT Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 12/37] MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 13/37] MIPS: JZ4740: register an irq_domain for the interrupt controller Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-28 10:46 ` James Hogan
2015-04-28 10:46 ` James Hogan
2015-04-24 13:17 ` [PATCH v4 14/37] MIPS: JZ4740: drop intc debugfs code Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-28 7:20 ` Lars-Peter Clausen
2015-04-24 13:17 ` [PATCH v4 15/37] MIPS: JZ4740: remove jz_intc_base global Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-27 22:35 ` James Hogan
2015-04-27 22:35 ` James Hogan
2015-04-24 13:17 ` [PATCH v4 16/37] MIPS: JZ4740: support >32 interrupts Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 17/37] MIPS: JZ4740: define IRQ numbers based on number of intc IRQs Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 18/37] MIPS: JZ4740: read intc base address from DT Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 19/37] MIPS: JZ4740: avoid JZ4740-specific naming Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 20/37] MIPS: JZ4740: support newer SoC interrupt controllers Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-28 11:03 ` James Hogan
2015-04-28 11:03 ` James Hogan
2015-04-24 13:17 ` [PATCH v4 21/37] irqchip: move Ingenic SoC intc driver to drivers/irqchip Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 22/37] MIPS: JZ4740: call jz4740_clock_init earlier Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 23/37] MIPS: JZ4740: replace use of jz4740_clock_bdata Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 24/37] devicetree: add Ingenic CGU binding documentation Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 25/37] clk: ingenic: add driver for Ingenic SoC CGU clocks Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-27 23:00 ` James Hogan
2015-04-27 23:00 ` James Hogan
2015-04-28 10:17 ` James Hogan
2015-04-28 10:17 ` James Hogan
2015-05-20 23:16 ` Stephen Boyd [this message]
2015-04-24 13:17 ` [PATCH v4 26/37] MIPS,clk: migrate JZ4740 to common clock framework Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-05-13 2:52 ` Michael Turquette
2015-05-13 2:52 ` Michael Turquette
2015-05-13 2:52 ` Michael Turquette
2015-05-13 2:52 ` Michael Turquette
2015-05-24 15:01 ` Paul Burton
2015-05-24 15:01 ` Paul Burton
2015-05-24 15:01 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 27/37] MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-05-13 2:56 ` [PATCH v4 27/37] MIPS, clk: " Michael Turquette
2015-05-13 2:56 ` Michael Turquette
2015-05-13 2:56 ` Michael Turquette
2015-04-24 13:17 ` [PATCH v4 28/37] MIPS,clk: move jz4740 UDC auto suspend functions " Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-05-13 3:06 ` [PATCH v4 28/37] MIPS, clk: " Michael Turquette
2015-05-13 3:06 ` Michael Turquette
2015-05-24 15:02 ` Paul Burton
2015-05-24 15:02 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 29/37] MIPS,clk: move jz4740 clock suspend,resume " Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 30/37] clk: ingenic: add JZ4780 CGU support Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-05-20 23:07 ` Stephen Boyd
2015-04-24 13:17 ` [PATCH v4 31/37] MIPS: JZ4740: remove clock.h Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 32/37] MIPS: JZ4740: only detect RAM size if not specified in DT Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 33/37] devicetree: document Ingenic SoC UART binding Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 34/37] serial: 8250_ingenic: support for Ingenic SoC UARTs Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 35/37] MIPS: JZ4740: use Ingenic SoC UART driver Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 36/37] MIPS: ingenic: initial JZ4780 support Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-28 10:36 ` James Hogan
2015-04-28 10:36 ` James Hogan
2015-04-28 10:36 ` James Hogan
2015-04-24 13:17 ` [PATCH v4 37/37] MIPS: ingenic: initial MIPS Creator CI20 support Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` Paul Burton
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150520231644.GZ31753@codeaurora.org \
--to=sboyd@codeaurora.org \
--cc=lars@metafoo.de \
--cc=linux-clk@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=mturquette@linaro.org \
--cc=paul.burton@imgtec.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.