From: Stephen Boyd <sboyd@codeaurora.org>
To: Rhyland Klein <rklein@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
Stephen Warren <swarren@wwwdotorg.org>,
Thierry Reding <thierry.reding@gmail.com>,
Alexandre Courbot <gnurou@gmail.com>,
Bill Huang <bilhuang@nvidia.com>,
Paul Walmsley <pwalmsley@nvidia.com>, Jim Lin <jilin@nvidia.com>,
Benson Leung <bleung@chromium.org>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 14/21] clk: tegra: pll: Adjust vco_min if SDM present
Date: Thu, 4 Jun 2015 11:52:59 -0700 [thread overview]
Message-ID: <20150604185259.GA676@codeaurora.org> (raw)
In-Reply-To: <1431451444-23155-16-git-send-email-rklein@nvidia.com>
On 05/12, Rhyland Klein wrote:
> From: Bill Huang <bilhuang@nvidia.com>
>
> This code makes use of the SDM fractional divider if present to
> contrain the allowable programming range of the PLL divider register
s/contrain/constrain/
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Mike Turquette
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Jim Lin <jilin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Benson Leung <bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v5 14/21] clk: tegra: pll: Adjust vco_min if SDM present
Date: Thu, 4 Jun 2015 11:52:59 -0700 [thread overview]
Message-ID: <20150604185259.GA676@codeaurora.org> (raw)
In-Reply-To: <1431451444-23155-16-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 05/12, Rhyland Klein wrote:
> From: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> This code makes use of the SDM fractional divider if present to
> contrain the allowable programming range of the PLL divider register
s/contrain/constrain/
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-06-04 18:52 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-12 17:23 [PATCH v5 00/21] Tegra210 Clock Support Rhyland Klein
2015-05-12 17:23 ` Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 01/21] clk: tegra: Update struct tegra_clk_pll_params kerneldoc Rhyland Klein
2015-05-12 17:23 ` Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 01/21] FROMLIST: " Rhyland Klein
2015-05-12 17:23 ` Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 02/21] clk: tegra: Modify tegra_audio_clk_init to accept more plls Rhyland Klein
2015-05-12 17:23 ` Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 03/21] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
2015-05-12 17:23 ` Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 04/21] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header Rhyland Klein
2015-05-12 21:52 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 05/21] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 06/21] clk: tegra: pll: update warning msg Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 07/21] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
2015-05-12 17:23 ` Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 08/21] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 09/21] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
2015-05-18 22:35 ` Benson Leung
2015-05-18 22:35 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 10/21] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
2015-05-12 17:23 ` Rhyland Klein
2015-05-13 0:01 ` Benson Leung
2015-05-13 0:01 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 11/21] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 12/21] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
2015-05-13 20:59 ` Benson Leung
2015-05-13 20:59 ` Benson Leung
2015-05-20 17:24 ` Rhyland Klein
2015-05-20 17:24 ` Rhyland Klein
2015-05-20 17:26 ` Benson Leung
2015-05-20 17:26 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 13/21] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
2015-05-12 17:23 ` Rhyland Klein
2015-05-13 22:04 ` Benson Leung
2015-05-13 22:04 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 14/21] clk: tegra: pll: Adjust vco_min if SDM present Rhyland Klein
2015-05-13 22:11 ` Benson Leung
2015-05-13 22:11 ` Benson Leung
2015-06-04 18:52 ` Stephen Boyd [this message]
2015-06-04 18:52 ` Stephen Boyd
2015-05-12 17:23 ` [PATCH v5 15/21] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
2015-05-12 17:23 ` Rhyland Klein
2015-05-13 22:20 ` Benson Leung
2015-05-13 22:20 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 16/21] clk: tegra: pll: Add Set_default logic Rhyland Klein
2015-05-14 0:04 ` Benson Leung
2015-05-20 17:20 ` Rhyland Klein
2015-05-20 17:20 ` Rhyland Klein
2015-05-12 17:24 ` [PATCH v5 17/21] clk: tegra: pll: Add logic for SS Rhyland Klein
2015-05-14 0:25 ` Benson Leung
2015-05-20 17:19 ` Rhyland Klein
2015-05-20 17:19 ` Rhyland Klein
2015-05-12 17:24 ` [PATCH v5 18/21] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Rhyland Klein
2015-05-14 0:29 ` Benson Leung
2015-05-14 0:29 ` Benson Leung
2015-05-12 17:24 ` [PATCH v5 19/21] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-05-13 20:36 ` Benson Leung
2015-05-14 19:37 ` Benson Leung
2015-05-25 8:19 ` Bill Huang
2015-05-25 8:19 ` Bill Huang
2015-05-25 8:19 ` Bill Huang
2015-05-12 17:24 ` [PATCH v5 20/21] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-05-12 17:24 ` Rhyland Klein
2015-05-14 20:23 ` Benson Leung
2015-05-20 17:17 ` Rhyland Klein
2015-05-20 17:17 ` Rhyland Klein
2015-05-20 9:47 ` Jim Lin
2015-05-20 9:47 ` Jim Lin
2015-05-20 17:16 ` Rhyland Klein
2015-05-20 17:16 ` Rhyland Klein
2015-05-12 17:24 ` [PATCH v5 21/21] clk: tegra: pll: Fix issues with rates for VCO PLLs Rhyland Klein
2015-05-14 20:02 ` Benson Leung
2015-05-14 20:02 ` Benson Leung
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